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a0090a0113
Also add glc bit to the scalar loads since they exist on VI and change the caching behavior. This currently has an assembler bug where the glc bit is incorrectly accepted on SI/CI which do not have it. llvm-svn: 285463
16 lines
557 B
ArmAsm
16 lines
557 B
ArmAsm
// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
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s_load_dwordx4 s[100:103], s[2:3], s4
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// VI: error: not a valid operand
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// SI: s_load_dwordx4 s[100:103], s[2:3], s4
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s_load_dwordx8 s[96:103], s[2:3], s4
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// VI: error: not a valid operand
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// SI: s_load_dwordx8 s[96:103], s[2:3], s4
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s_load_dwordx16 s[88:103], s[2:3], s4
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// VI: error: not a valid operand
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// SI: s_load_dwordx16 s[88:103], s[2:3], s4
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