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66 lines
1.9 KiB
C++
66 lines
1.9 KiB
C++
//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Contains the definition of a TargetInstrInfo class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_OPERAND_ENUM
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#include "AMDGPUGenInstrInfo.inc"
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namespace llvm {
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class AMDGPUSubtarget;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
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private:
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const AMDGPUSubtarget &ST;
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virtual void anchor();
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public:
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explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
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bool enableClusterLoads() const override;
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bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const override;
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/// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
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/// Return -1 if the target-specific opcode for the pseudo instruction does
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/// not exist. If Opcode is not a pseudo instruction, this is identity.
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int pseudoToMCOpcode(int Opcode) const;
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/// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
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/// equivalent opcode that writes \p Channels Channels.
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int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
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};
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namespace AMDGPU {
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LLVM_READONLY
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int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
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} // End namespace AMDGPU
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} // End llvm namespace
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#endif
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