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https://github.com/RPCS3/llvm-mirror.git
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b2fe6dcbc2
Such attributes can either be unset, or set to "true" or "false" (as string).
throughout the codebase, this led to inelegant checks ranging from
if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
to
if (Fn->hasAttribute("no-jump-tables") && Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
Introduce a getValueAsBool that normalize the check, with the following
behavior:
no attributes or attribute set to "false" => return false
attribute set to "true" => return true
Differential Revision: https://reviews.llvm.org/D99299
459 lines
18 KiB
C++
459 lines
18 KiB
C++
//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Hexagon target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonTargetMachine.h"
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#include "Hexagon.h"
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#include "HexagonISelLowering.h"
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#include "HexagonLoopIdiomRecognition.h"
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#include "HexagonMachineScheduler.h"
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#include "HexagonTargetObjectFile.h"
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#include "HexagonTargetTransformInfo.h"
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#include "HexagonVectorLoopCarriedReuse.h"
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#include "TargetInfo/HexagonTargetInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Passes/PassBuilder.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Transforms/IPO/PassManagerBuilder.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
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cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
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static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
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cl::init(true), cl::desc("Enable RDF-based optimizations"));
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static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
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cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
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static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon Addressing Mode Optimization"));
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static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon CFG Optimization"));
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static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
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cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
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static cl::opt<bool> DisableStoreWidening("disable-store-widen",
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cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
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static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
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cl::init(true), cl::Hidden, cl::ZeroOrMore,
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cl::desc("Early expansion of MUX"));
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static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
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cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
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static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
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cl::Hidden, cl::desc("Generate \"insert\" instructions"));
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static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
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cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
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static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
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cl::Hidden, cl::desc("Generate \"extract\" instructions"));
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static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
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cl::desc("Enable converting conditional transfers into MUX instructions"));
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static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
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cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
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"predicate instructions"));
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static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
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cl::init(false), cl::Hidden, cl::ZeroOrMore,
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cl::desc("Enable loop data prefetch on Hexagon"));
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static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
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cl::desc("Disable splitting double registers"));
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static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
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cl::Hidden, cl::desc("Bit simplification"));
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static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
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cl::Hidden, cl::desc("Loop rescheduling"));
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static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
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cl::Hidden, cl::desc("Disable backend optimizations"));
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static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Enable Hexagon Vector print instr pass"));
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static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
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cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
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static cl::opt<bool> EnableVectorCombine("hexagon-vector-combine", cl::Hidden,
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cl::ZeroOrMore, cl::init(true), cl::desc("Enable HVX vector combining"));
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static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
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cl::Hidden, cl::ZeroOrMore, cl::init(true),
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cl::desc("Simplify the CFG after atomic expansion pass"));
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static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
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cl::ZeroOrMore, cl::init(true),
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cl::desc("Enable instsimplify"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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/// library. In particular, it seems that it is not possible to get
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/// things to work on Win32 without this. Though it is unused, do not
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/// remove it.
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extern "C" int HexagonTargetMachineModule;
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int HexagonTargetMachineModule = 0;
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static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
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ScheduleDAGMILive *DAG =
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new VLIWMachineScheduler(C, std::make_unique<ConvergingVLIWScheduler>());
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DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
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DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
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DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
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DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
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return DAG;
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}
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static MachineSchedRegistry
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SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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createVLIWMachineSched);
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namespace llvm {
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extern char &HexagonExpandCondsetsID;
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void initializeHexagonBitSimplifyPass(PassRegistry&);
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void initializeHexagonConstExtendersPass(PassRegistry&);
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void initializeHexagonConstPropagationPass(PassRegistry&);
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void initializeHexagonEarlyIfConversionPass(PassRegistry&);
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void initializeHexagonExpandCondsetsPass(PassRegistry&);
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void initializeHexagonGenMuxPass(PassRegistry&);
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void initializeHexagonHardwareLoopsPass(PassRegistry&);
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void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
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void initializeHexagonNewValueJumpPass(PassRegistry&);
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void initializeHexagonOptAddrModePass(PassRegistry&);
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void initializeHexagonPacketizerPass(PassRegistry&);
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void initializeHexagonRDFOptPass(PassRegistry&);
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void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
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void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
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void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
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void initializeHexagonVExtractPass(PassRegistry&);
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Pass *createHexagonLoopIdiomPass();
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Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
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FunctionPass *createHexagonBitSimplify();
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FunctionPass *createHexagonBranchRelaxation();
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FunctionPass *createHexagonCallFrameInformation();
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FunctionPass *createHexagonCFGOptimizer();
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FunctionPass *createHexagonCommonGEP();
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FunctionPass *createHexagonConstExtenders();
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FunctionPass *createHexagonConstPropagationPass();
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FunctionPass *createHexagonCopyToCombine();
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FunctionPass *createHexagonEarlyIfConversion();
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FunctionPass *createHexagonFixupHwLoops();
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FunctionPass *createHexagonGenExtract();
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FunctionPass *createHexagonGenInsert();
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FunctionPass *createHexagonGenMux();
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FunctionPass *createHexagonGenPredicate();
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FunctionPass *createHexagonHardwareLoops();
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FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createHexagonLoopRescheduling();
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FunctionPass *createHexagonNewValueJump();
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FunctionPass *createHexagonOptAddrMode();
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FunctionPass *createHexagonOptimizeSZextends();
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FunctionPass *createHexagonPacketizer(bool Minimal);
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FunctionPass *createHexagonPeephole();
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FunctionPass *createHexagonRDFOpt();
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FunctionPass *createHexagonSplitConst32AndConst64();
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FunctionPass *createHexagonSplitDoubleRegs();
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FunctionPass *createHexagonStoreWidening();
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FunctionPass *createHexagonVectorCombineLegacyPass();
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FunctionPass *createHexagonVectorPrint();
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FunctionPass *createHexagonVExtract();
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} // end namespace llvm;
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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return RM.getValueOr(Reloc::Static);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
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// Register the target.
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RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializeHexagonBitSimplifyPass(PR);
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initializeHexagonConstExtendersPass(PR);
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initializeHexagonConstPropagationPass(PR);
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initializeHexagonEarlyIfConversionPass(PR);
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initializeHexagonGenMuxPass(PR);
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initializeHexagonHardwareLoopsPass(PR);
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initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
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initializeHexagonNewValueJumpPass(PR);
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initializeHexagonOptAddrModePass(PR);
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initializeHexagonPacketizerPass(PR);
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initializeHexagonRDFOptPass(PR);
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initializeHexagonSplitDoubleRegsPass(PR);
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initializeHexagonVectorCombineLegacyPass(PR);
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initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
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initializeHexagonVExtractPass(PR);
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}
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HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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// Specify the vector alignment explicitly. For v512x1, the calculated
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// alignment would be 512*alignment(i1), which is 512 bytes, instead of
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// the required minimum of 64 bytes.
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: LLVMTargetMachine(
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T,
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"e-m:e-p:32:32:32-a:0-n16:32-"
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"i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
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"v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
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TT, CPU, FS, Options, getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CM, CodeModel::Small),
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(HexagonNoOpt ? CodeGenOpt::None : OL)),
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TLOF(std::make_unique<HexagonTargetObjectFile>()) {
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initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
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initAsmInfo();
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}
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const HexagonSubtarget *
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HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
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AttributeList FnAttrs = F.getAttributes();
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Attribute CPUAttr =
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FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
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Attribute FSAttr =
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FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
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std::string CPU =
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CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
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std::string FS =
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FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
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// Append the preexisting target features last, so that +mattr overrides
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// the "unsafe-fp-math" function attribute.
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// Creating a separate target feature is not strictly necessary, it only
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// exists to make "unsafe-fp-math" force creating a new subtarget.
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if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
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FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
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}
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return I.get();
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}
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void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
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PMB.addExtension(
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PassManagerBuilder::EP_LateLoopOptimizations,
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[&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
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PM.add(createHexagonLoopIdiomPass());
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});
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PMB.addExtension(
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PassManagerBuilder::EP_LoopOptimizerEnd,
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[&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
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PM.add(createHexagonVectorLoopCarriedReuseLegacyPass());
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});
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}
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void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
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bool DebugPassManager) {
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PB.registerLateLoopOptimizationsEPCallback(
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[=](LoopPassManager &LPM, PassBuilder::OptimizationLevel Level) {
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LPM.addPass(HexagonLoopIdiomRecognitionPass());
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});
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PB.registerLoopOptimizerEndEPCallback(
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[=](LoopPassManager &LPM, PassBuilder::OptimizationLevel Level) {
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LPM.addPass(HexagonVectorLoopCarriedReusePass());
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});
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}
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TargetTransformInfo
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HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
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return TargetTransformInfo(HexagonTTIImpl(this, F));
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}
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HexagonTargetMachine::~HexagonTargetMachine() {}
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namespace {
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/// Hexagon Code Generator Pass Configuration Options.
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class HexagonPassConfig : public TargetPassConfig {
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public:
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HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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HexagonTargetMachine &getHexagonTargetMachine() const {
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return getTM<HexagonTargetMachine>();
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}
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override {
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return createVLIWMachineSched(C);
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreRegAlloc() override;
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void addPostRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new HexagonPassConfig(*this, PM);
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}
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void HexagonPassConfig::addIRPasses() {
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TargetPassConfig::addIRPasses();
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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if (!NoOpt) {
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if (EnableInstSimplify)
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addPass(createInstSimplifyLegacyPass());
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addPass(createDeadCodeEliminationPass());
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}
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addPass(createAtomicExpandPass());
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if (!NoOpt) {
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if (EnableInitialCFGCleanup)
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addPass(createCFGSimplificationPass(SimplifyCFGOptions()
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.forwardSwitchCondToPhi(true)
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.convertSwitchToLookupTable(true)
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.needCanonicalLoops(false)
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.hoistCommonInsts(true)
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.sinkCommonInsts(true)));
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if (EnableLoopPrefetch)
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addPass(createLoopDataPrefetchPass());
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if (EnableVectorCombine)
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addPass(createHexagonVectorCombineLegacyPass());
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if (EnableCommGEP)
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addPass(createHexagonCommonGEP());
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// Replace certain combinations of shifts and ands with extracts.
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if (EnableGenExtract)
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addPass(createHexagonGenExtract());
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}
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}
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bool HexagonPassConfig::addInstSelector() {
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HexagonTargetMachine &TM = getHexagonTargetMachine();
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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if (!NoOpt)
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addPass(createHexagonOptimizeSZextends());
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addPass(createHexagonISelDag(TM, getOptLevel()));
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if (!NoOpt) {
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if (EnableVExtractOpt)
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addPass(createHexagonVExtract());
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// Create logical operations on predicate registers.
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if (EnableGenPred)
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addPass(createHexagonGenPredicate());
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// Rotate loops to expose bit-simplification opportunities.
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if (EnableLoopResched)
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addPass(createHexagonLoopRescheduling());
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// Split double registers.
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if (!DisableHSDR)
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addPass(createHexagonSplitDoubleRegs());
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// Bit simplification.
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if (EnableBitSimplify)
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addPass(createHexagonBitSimplify());
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addPass(createHexagonPeephole());
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// Constant propagation.
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if (!DisableHCP) {
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addPass(createHexagonConstPropagationPass());
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addPass(&UnreachableMachineBlockElimID);
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}
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if (EnableGenInsert)
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addPass(createHexagonGenInsert());
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if (EnableEarlyIf)
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addPass(createHexagonEarlyIfConversion());
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}
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return false;
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}
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void HexagonPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None) {
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if (EnableCExtOpt)
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addPass(createHexagonConstExtenders());
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if (EnableExpandCondsets)
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insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
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if (!DisableStoreWidening)
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addPass(createHexagonStoreWidening());
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if (!DisableHardwareLoops)
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addPass(createHexagonHardwareLoops());
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}
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if (TM->getOptLevel() >= CodeGenOpt::Default)
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addPass(&MachinePipelinerID);
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}
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void HexagonPassConfig::addPostRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None) {
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if (EnableRDFOpt)
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addPass(createHexagonRDFOpt());
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if (!DisableHexagonCFGOpt)
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addPass(createHexagonCFGOptimizer());
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if (!DisableAModeOpt)
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addPass(createHexagonOptAddrMode());
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}
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}
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void HexagonPassConfig::addPreSched2() {
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addPass(createHexagonCopyToCombine());
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if (getOptLevel() != CodeGenOpt::None)
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addPass(&IfConverterID);
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addPass(createHexagonSplitConst32AndConst64());
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}
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void HexagonPassConfig::addPreEmitPass() {
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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if (!NoOpt)
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addPass(createHexagonNewValueJump());
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addPass(createHexagonBranchRelaxation());
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if (!NoOpt) {
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if (!DisableHardwareLoops)
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addPass(createHexagonFixupHwLoops());
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// Generate MUX from pairs of conditional transfers.
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if (EnableGenMux)
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addPass(createHexagonGenMux());
|
|
}
|
|
|
|
// Packetization is mandatory: it handles gather/scatter at all opt levels.
|
|
addPass(createHexagonPacketizer(NoOpt), false);
|
|
|
|
if (EnableVectorPrint)
|
|
addPass(createHexagonVectorPrint(), false);
|
|
|
|
// Add CFI instructions if necessary.
|
|
addPass(createHexagonCallFrameInformation(), false);
|
|
}
|