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llvm-mirror/test/CodeGen/AArch64/dp1.ll
David Blaikie ab043ff680 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00

153 lines
4.4 KiB
LLVM

; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
@var32 = global i32 0
@var64 = global i64 0
define void @rev_i32() {
; CHECK-LABEL: rev_i32:
%val0_tmp = load i32, i32* @var32
%val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val1_tmp, i32* @var32
ret void
}
define void @rev_i64() {
; CHECK-LABEL: rev_i64:
%val0_tmp = load i64, i64* @var64
%val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val1_tmp, i64* @var64
ret void
}
define void @rev32_i64() {
; CHECK-LABEL: rev32_i64:
%val0_tmp = load i64, i64* @var64
%val1_tmp = shl i64 %val0_tmp, 32
%val5_tmp = sub i64 64, 32
%val2_tmp = lshr i64 %val0_tmp, %val5_tmp
%val3_tmp = or i64 %val1_tmp, %val2_tmp
%val4_tmp = call i64 @llvm.bswap.i64(i64 %val3_tmp)
; CHECK: rev32 {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val4_tmp, i64* @var64
ret void
}
define void @rev16_i32() {
; CHECK-LABEL: rev16_i32:
%val0_tmp = load i32, i32* @var32
%val1_tmp = shl i32 %val0_tmp, 16
%val2_tmp = lshr i32 %val0_tmp, 16
%val3_tmp = or i32 %val1_tmp, %val2_tmp
%val4_tmp = call i32 @llvm.bswap.i32(i32 %val3_tmp)
; CHECK: rev16 {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @clz_zerodef_i32() {
; CHECK-LABEL: clz_zerodef_i32:
%val0_tmp = load i32, i32* @var32
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @clz_zerodef_i64() {
; CHECK-LABEL: clz_zerodef_i64:
%val0_tmp = load i64, i64* @var64
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val4_tmp, i64* @var64
ret void
}
define void @clz_zeroundef_i32() {
; CHECK-LABEL: clz_zeroundef_i32:
%val0_tmp = load i32, i32* @var32
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @clz_zeroundef_i64() {
; CHECK-LABEL: clz_zeroundef_i64:
%val0_tmp = load i64, i64* @var64
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val4_tmp, i64* @var64
ret void
}
define void @cttz_zerodef_i32() {
; CHECK-LABEL: cttz_zerodef_i32:
%val0_tmp = load i32, i32* @var32
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @cttz_zerodef_i64() {
; CHECK-LABEL: cttz_zerodef_i64:
%val0_tmp = load i64, i64* @var64
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
store volatile i64 %val4_tmp, i64* @var64
ret void
}
define void @cttz_zeroundef_i32() {
; CHECK-LABEL: cttz_zeroundef_i32:
%val0_tmp = load i32, i32* @var32
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @cttz_zeroundef_i64() {
; CHECK-LABEL: cttz_zeroundef_i64:
%val0_tmp = load i64, i64* @var64
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
store volatile i64 %val4_tmp, i64* @var64
ret void
}
; These two are just compilation tests really: the operation's set to Expand in
; ISelLowering.
define void @ctpop_i32() {
; CHECK-LABEL: ctpop_i32:
%val0_tmp = load i32, i32* @var32
%val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @ctpop_i64() {
; CHECK-LABEL: ctpop_i64:
%val0_tmp = load i64, i64* @var64
%val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
store volatile i64 %val4_tmp, i64* @var64
ret void
}
declare i32 @llvm.bswap.i32(i32)
declare i64 @llvm.bswap.i64(i64)
declare i32 @llvm.ctlz.i32 (i32, i1)
declare i64 @llvm.ctlz.i64 (i64, i1)
declare i32 @llvm.cttz.i32 (i32, i1)
declare i64 @llvm.cttz.i64 (i64, i1)
declare i32 @llvm.ctpop.i32 (i32)
declare i64 @llvm.ctpop.i64 (i64)