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ce9abb7e3a
Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
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18 lines
418 B
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* Automatically generated file, do not edit! *
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.. _amdgpu_synid7_vsrc64_0:
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vsrc
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===========================
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Instruction input.
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*Size:* 2 dwords.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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