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a4a46c15fe
Summary:
Two exceptions to this:
test/CodeGen/Mips/octeon.ll
test/CodeGen/Mips/octeon_popcnt.ll
these test extensions to MIPS64
One test is altered for MIPS-IV:
test/CodeGen/Mips/mips64countleading.ll
Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests
that dclo/dclz are not emitted.
Four tests fail and are not in this patch:
test/CodeGen/Mips/abicalls.ll
test/CodeGen/Mips/fcopysign-f32-f64.ll
test/CodeGen/Mips/fcopysign.ll
test/CodeGen/Mips/stack-alignment.ll
Depends on D3343
Reviewers: matheusalmeida, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3344
llvm-svn: 206185
50 lines
1.2 KiB
LLVM
50 lines
1.2 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
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; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
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@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
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@i3 = common global i32* null, align 4
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; 32-LABEL: test_float_int_:
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; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
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; 32: cvt.s.w $f{{[0-9]+}}, $f[[R0]]
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define float @test_float_int_(i32 %a) {
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entry:
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%conv = sitofp i32 %a to float
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ret float %conv
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}
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; 32-LABEL: test_double_int_:
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; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
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; 32: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
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; 64-LABEL: test_double_int_:
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; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
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; 64: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
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define double @test_double_int_(i32 %a) {
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entry:
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%conv = sitofp i32 %a to double
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ret double %conv
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}
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; 64-LABEL: test_float_LL_:
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; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
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; 64: cvt.s.l $f{{[0-9]+}}, $f[[R0]]
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define float @test_float_LL_(i64 %a) {
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entry:
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%conv = sitofp i64 %a to float
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ret float %conv
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}
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; 64-LABEL: test_double_LL_:
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; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
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; 64: cvt.d.l $f{{[0-9]+}}, $f[[R0]]
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define double @test_double_LL_(i64 %a) {
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entry:
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%conv = sitofp i64 %a to double
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ret double %conv
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}
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