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I had hoped that I could have some ``` .. code-block:: MIR ``` sections for MIR examples which causes a warning about pygments not supporting it but we have warnings treated as errors
96 lines
3.0 KiB
ReStructuredText
96 lines
3.0 KiB
ReStructuredText
.. _irtranslator:
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IRTranslator
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============
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.. contents::
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:local:
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This pass translates the input LLVM-IR ``Function`` to a GMIR
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``MachineFunction``. This is typically a direct translation but does
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occasionally get a bit more involved. For example:
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.. code-block:: llvm
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%2 = add i32 %0, %1
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becomes:
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.. code-block:: none
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%2:_(s32) = G_ADD %0:_(s32), %1:_(s32)
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whereas
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.. code-block:: llvm
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call i32 @puts(i8* %cast210)
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is translated according to the ABI rules of the target.
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.. note::
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The currently implemented portion of the :doc:`../LangRef` is sufficient for
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many compilations but it is not 100% complete. Users seeking to compile
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LLVM-IR containing some of the rarer features may need to implement the
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translation.
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Target Intrinsics
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-----------------
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There has been some (off-list) debate about whether to add target hooks for
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translating target intrinsics. Among those who discussed it, it was generally
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agreed that the IRTranslator should be able to lower target intrinsics in a
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customizable way but no work has happened to implement this at the time of
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writing.
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.. _translator-call-lower:
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Translating Function Calls
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--------------------------
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The ``IRTranslator`` also implements the ABI's calling convention by lowering
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calls, returns, and arguments to the appropriate physical register usage and
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instruction sequences. This is achieved using the ``CallLowering``
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implementation,
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.. _irtranslator-aggregates:
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Aggregates
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^^^^^^^^^^
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.. caution::
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This has changed since it was written and is no longer accurate. It has not
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been refreshed in this pass of improving the documentation as I haven't
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worked much in this part of the codebase and it should have attention from
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someone more knowledgeable about it.
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Aggregates are lowered to a single scalar vreg.
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This differs from SelectionDAG's multiple vregs via ``GetValueVTs``.
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``TODO``:
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As some of the bits are undef (padding), we should consider augmenting the
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representation with additional metadata (in effect, caching computeKnownBits
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information on vregs).
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See `PR26161 <http://llvm.org/PR26161>`_: [GlobalISel] Value to vreg during
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IR to MachineInstr translation for aggregate type
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.. _irtranslator-constants:
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Translation of Constants
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------------------------
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Constant operands are translated as a use of a virtual register that is defined
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by a ``G_CONSTANT`` or ``G_FCONSTANT`` instruction. These instructions are
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placed in the entry block to allow them to be subject to the continuous CSE
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implementation (``CSEMIRBuilder``). Their debug location information is removed
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to prevent this from confusing debuggers.
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This is beneficial as it allows us to fold constants into immediate operands
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during :ref:`instructionselect`, while still avoiding redundant materializations
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for expensive non-foldable constants. However, this can lead to unnecessary
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spills and reloads in an -O0 pipeline, as these virtual registers can have long
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live ranges. This can be mitigated by running a `localizer <https://github.com/llvm/llvm-project/blob/master/llvm/lib/CodeGen/GlobalISel/Localizer.cpp>`_
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after the translator.
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