mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
68985b72e3
PowerPC assembly code in the wild, so it seems, has things like this: bc+ 12, 28, .L9 This is a bit odd because the '+' here becomes part of the BO field, and the BO field is otherwise the first operand. Nevertheless, the ISA specification does clearly say that the +- hint syntax applies to all conditional-branch mnemonics (that test either CTR or a condition register, although not the forms which check both), both basic and extended, so this is supposed to be valid. This introduces some asm-parser-only definitions which take only the upper three bits from the specified BO value, and the lower two bits are implied by the +- suffix (via some associated aliases). Fixes PR23646. llvm-svn: 280571 |
||
|---|---|---|
| .. | ||
| dcbt.s | ||
| deprecated-p7.s | ||
| htm.s | ||
| lcomm.s | ||
| lit.local.cfg | ||
| ppc32-ba.s | ||
| ppc64-abiversion.s | ||
| ppc64-encoding-4xx.s | ||
| ppc64-encoding-6xx.s | ||
| ppc64-encoding-bookII.s | ||
| ppc64-encoding-bookIII.s | ||
| ppc64-encoding-e500.s | ||
| ppc64-encoding-ext.s | ||
| ppc64-encoding-fp.s | ||
| ppc64-encoding-p8vector.s | ||
| ppc64-encoding-spe.s | ||
| ppc64-encoding-vmx.s | ||
| ppc64-encoding.s | ||
| ppc64-errors.s | ||
| ppc64-fixup-apply.s | ||
| ppc64-fixup-explicit.s | ||
| ppc64-fixups.s | ||
| ppc64-initial-cfa.s | ||
| ppc64-localentry-error1.s | ||
| ppc64-localentry-error2.s | ||
| ppc64-localentry.s | ||
| ppc64-operands.s | ||
| ppc64-regs.s | ||
| ppc64-relocs-01.s | ||
| ppc64-tls-relocs-01.s | ||
| ppc-llong.s | ||
| ppc-machine.s | ||
| ppc-nop.s | ||
| ppc-reloc.s | ||
| ppc-word.s | ||
| pr24686.s | ||
| qpx.s | ||
| st-other-crash.s | ||
| tls-gd-obj.s | ||
| tls-ie-obj.s | ||
| tls-ld-obj.s | ||
| vsx.s | ||