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https://github.com/RPCS3/llvm-mirror.git
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30a743add7
Summary: They correspond to BUFFER_LOAD/STORE_DWORD[_X2,X3,X4] and mostly behave like llvm.amdgcn.buffer.load/store.format. They will be used by Mesa for SSBO and atomic counters at least when robust buffer access behavior is desired. (These instructions perform no format conversion and do buffer range checking per component.) As a side effect of sharing patterns with llvm.amdgcn.buffer.store.format, it has become trivial to add support for the f32 and v2f32 variants of that intrinsic, so the patch does so. Also DAG-ify (and fix) some tests that I noticed intermittent failures in while developing this patch. Some tests were (temporarily) adjusted for the required mayLoad/hasSideEffects changes to the BUFFER_STORE_DWORD* instructions. See also http://reviews.llvm.org/D18291. Reviewers: arsenm, tstellarAMD, mareko Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18292 llvm-svn: 266126
191 lines
7.6 KiB
LLVM
191 lines
7.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}load_i8_to_f32:
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; SI: buffer_load_ubyte [[LOADREG:v[0-9]+]],
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; SI-NOT: bfe
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; SI-NOT: lshr
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; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]]
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; SI: buffer_store_dword [[CONV]],
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define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
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%load = load i8, i8 addrspace(1)* %in, align 1
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%cvt = uitofp i8 %load to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}load_v2i8_to_v2f32:
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; SI: buffer_load_ushort [[LOADREG:v[0-9]+]],
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; SI-NOT: bfe
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; SI-NOT: lshr
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; SI-NOT: and
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; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
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; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <2 x i8>, <2 x i8> addrspace(1)* %in, align 2
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%cvt = uitofp <2 x i8> %load to <2 x float>
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store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}load_v3i8_to_v3f32:
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; SI-NOT: bfe
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; SI-NOT: v_cvt_f32_ubyte3_e32
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; SI-DAG: v_cvt_f32_ubyte2_e32
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; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]],
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; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]],
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; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 4
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%cvt = uitofp <3 x i8> %load to <3 x float>
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store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}load_v4i8_to_v4f32:
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; SI: buffer_load_dword [[LOADREG:v[0-9]+]]
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; SI-NOT: bfe
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; SI-NOT: lshr
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; SI-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
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; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]]
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; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
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; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
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%cvt = uitofp <4 x i8> %load to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; This should not be adding instructions to shift into the correct
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; position in the word for the component.
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; SI-LABEL: {{^}}load_v4i8_to_v4f32_unaligned:
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; SI: buffer_load_ubyte [[LOADREG3:v[0-9]+]]
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; SI: buffer_load_ubyte [[LOADREG2:v[0-9]+]]
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; SI: buffer_load_ubyte [[LOADREG1:v[0-9]+]]
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; SI: buffer_load_ubyte [[LOADREG0:v[0-9]+]]
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; SI-NOT: v_lshlrev_b32
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; SI-NOT: v_or_b32
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; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG0]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, [[LOADREG1]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, [[LOADREG2]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]], [[LOADREG3]]
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; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1
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%cvt = uitofp <4 x i8> %load to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; XXX - This should really still be able to use the v_cvt_f32_ubyte0
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; for each component, but computeKnownBits doesn't handle vectors very
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; well.
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; SI-LABEL: {{^}}load_v4i8_to_v4f32_2_uses:
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: v_cvt_f32_ubyte0_e32
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; SI: v_cvt_f32_ubyte0_e32
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; SI: v_cvt_f32_ubyte0_e32
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; SI: v_cvt_f32_ubyte0_e32
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; XXX - replace with this when v4i8 loads aren't scalarized anymore.
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; XSI: buffer_load_dword
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; XSI: v_cvt_f32_u32_e32
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; XSI: v_cvt_f32_u32_e32
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; XSI: v_cvt_f32_u32_e32
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; XSI: v_cvt_f32_u32_e32
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; SI: s_endpgm
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define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
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%cvt = uitofp <4 x i8> %load to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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%add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load
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store <4 x i8> %add, <4 x i8> addrspace(1)* %out2, align 4
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ret void
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}
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; Make sure this doesn't crash.
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; SI-LABEL: {{^}}load_v7i8_to_v7f32:
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; SI: s_endpgm
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define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <7 x i8>, <7 x i8> addrspace(1)* %in, align 1
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%cvt = uitofp <7 x i8> %load to <7 x float>
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store <7 x float> %cvt, <7 x float> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}load_v8i8_to_v8f32:
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; SI: buffer_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}},
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; SI-NOT: bfe
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; SI-NOT: lshr
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; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]]
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; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]]
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; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]]
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; SI-NOT: bfe
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; SI-NOT: lshr
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; SI: buffer_store_dwordx4
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; SI: buffer_store_dwordx4
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define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <8 x i8>, <8 x i8> addrspace(1)* %in, align 8
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%cvt = uitofp <8 x i8> %load to <8 x float>
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store <8 x float> %cvt, <8 x float> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}i8_zext_inreg_i32_to_f32:
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; SI: buffer_load_dword [[LOADREG:v[0-9]+]],
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; SI: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 2, [[LOADREG]]
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; SI-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]]
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; SI: buffer_store_dword [[CONV]],
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define void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%load = load i32, i32 addrspace(1)* %in, align 4
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%add = add i32 %load, 2
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%inreg = and i32 %add, 255
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%cvt = uitofp i32 %inreg to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}i8_zext_inreg_hi1_to_f32:
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define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%load = load i32, i32 addrspace(1)* %in, align 4
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%inreg = and i32 %load, 65280
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%shr = lshr i32 %inreg, 8
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%cvt = uitofp i32 %shr to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; We don't get these ones because of the zext, but instcombine removes
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; them so it shouldn't really matter.
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define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
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%load = load i8, i8 addrspace(1)* %in, align 1
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%ext = zext i8 %load to i32
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%cvt = uitofp i32 %ext to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1
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%ext = zext <4 x i8> %load to <4 x i32>
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%cvt = uitofp <4 x i32> %ext to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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