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llvm-mirror/test/CodeGen/Mips/sb1.ll
Daniel Sanders c168815f4b [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.
Summary:
The -mcpu=mips16 option caused the Integrated Assembler to crash because
it couldn't figure out the architecture revision number to write to the
.MIPS.abiflags section. This CPU definition has been removed because, like
microMIPS, MIPS16 is an ASE to a base architecture.

Reviewers: vkalintiris

Subscribers: rkotler, llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D13656

llvm-svn: 250407
2015-10-15 14:34:23 +00:00

21 lines
677 B
LLVM

; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 97, align 4
@c = common global i8 0, align 1
@.str = private unnamed_addr constant [8 x i8] c"%i %c \0A\00", align 1
define i32 @main() nounwind {
entry:
%0 = load i32, i32* @i, align 4
%conv = trunc i32 %0 to i8
store i8 %conv, i8* @c, align 1
%1 = load i32, i32* @i, align 4
%2 = load i8, i8* @c, align 1
%conv1 = sext i8 %2 to i32
; 16: sb ${{[0-9]+}}, 0(${{[0-9]+}})
%call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %1, i32 %conv1)
ret i32 0
}
declare i32 @printf(i8*, ...)