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e0d2002cc3
Vector imm setting instructions like XXLXORz/XXLXORspz/XXLXORdpz Should behave like LI8. We should set corresponding flags to allow rematerialization and other opts in LICM, RA, Scheduling etc. Differential Revision: https://reviews.llvm.org/D58645 llvm-svn: 355948
43 lines
1.5 KiB
LLVM
43 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
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define float @floatundisf(i64 %a) {
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; CHECK-LABEL: floatundisf:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxlxor f1, f1, f1
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; CHECK-NEXT: bclr 12, 4*cr5+lt, 0
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; CHECK-NEXT: # %bb.1: # %sw.epilog
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; CHECK-NEXT: addi r3, r3, 1
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; CHECK-NEXT: li r5, 2
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; CHECK-NEXT: andis. r4, r3, 1024
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; CHECK-NEXT: li r4, 3
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; CHECK-NEXT: isel r4, r5, r4, eq
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; CHECK-NEXT: srd r3, r3, r4
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; CHECK-NEXT: rlwinm r3, r3, 0, 9, 31
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; CHECK-NEXT: mtvsrd f0, r3
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; CHECK-NEXT: xxsldwi vs0, vs0, vs0, 1
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; CHECK-NEXT: xscvspdpn f1, vs0
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; CHECK-NEXT: blr
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entry:
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br i1 undef, label %return, label %sw.epilog
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sw.epilog: ; preds = %entry
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%or14 = or i64 0, %a
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%inc = add i64 %or14, 1
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%and16 = and i64 %inc, 67108864
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%tobool = icmp eq i64 %and16, 0
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%tmp.select.v = select i1 %tobool, i64 2, i64 3
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%tmp.select = lshr i64 %inc, %tmp.select.v
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%conv26 = trunc i64 %tmp.select to i32
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%and27 = and i32 %conv26, 8388607
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%or28 = or i32 0, %and27
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%0 = bitcast i32 %or28 to float
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br label %return
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return: ; preds = %sw.epilog, %entry
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%retval.0 = phi float [ %0, %sw.epilog ], [ 0.000000e+00, %entry ]
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ret float %retval.0
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}
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