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699d18eb82
Fix assert about using an undefined physical register in machine instruction verify pass. The reason is that register flag undef is missing when doing transformation from If Conversion Pass. ``` Bad machine code: Using an undefined physical register - function: func_65 - basic block: %bb.0 entry (0x10024740738) - instruction: BCLR killed $cr5lt, implicit $lr8, implicit $rm, implicit undef $x3 - operand 0: killed $cr5lt LLVM ERROR: Found 1 machine code errors. ``` There are also other existing testcases with same issue. So I add -verify-machineinstrs option to open verifying. Differential Revision: https://reviews.llvm.org/D55408 llvm-svn: 348566
47 lines
1.6 KiB
LLVM
47 lines
1.6 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
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target triple = "powerpc-montavista-linux-gnuspe"
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%struct.__va_list_tag.0.9.18.23.32.41.48.55.62.67.72.77.82.87.90.93.96.101.105 = type { i8, i8, i16, i8*, i8* }
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define fastcc void @test1(%struct.__va_list_tag.0.9.18.23.32.41.48.55.62.67.72.77.82.87.90.93.96.101.105* %args) {
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entry:
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br i1 undef, label %repeat, label %maxlen_reached
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repeat: ; preds = %entry
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switch i32 undef, label %sw.bb323 [
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i32 77, label %sw.bb72
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i32 111, label %sw.bb309
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i32 80, label %sw.bb313
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i32 117, label %sw.bb326
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i32 88, label %sw.bb321
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]
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sw.bb72: ; preds = %repeat
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unreachable
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sw.bb309: ; preds = %repeat
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unreachable
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sw.bb313: ; preds = %repeat
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unreachable
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sw.bb321: ; preds = %repeat
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unreachable
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sw.bb323: ; preds = %repeat
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%0 = va_arg %struct.__va_list_tag.0.9.18.23.32.41.48.55.62.67.72.77.82.87.90.93.96.101.105* %args, i32
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unreachable
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sw.bb326: ; preds = %repeat
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unreachable
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maxlen_reached: ; preds = %entry
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ret void
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}
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; If the SD nodes are not cleaup up correctly, then this can fail to compile
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; with an error like: Cannot select: ch = setlt [ID=6]
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; CHECK: @test1
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