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e0d2002cc3
Vector imm setting instructions like XXLXORz/XXLXORspz/XXLXORdpz Should behave like LI8. We should set corresponding flags to allow rematerialization and other opts in LICM, RA, Scheduling etc. Differential Revision: https://reviews.llvm.org/D58645 llvm-svn: 355948
57 lines
1.8 KiB
LLVM
57 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \
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; RUN: FileCheck %s --implicit-check-not=mtctr --implicit-check-not=bdnz
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$test = comdat any
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; No CTR loop due to frem (since it is always a call).
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define void @test() #0 comdat {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r29, -24
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; CHECK-NEXT: .cfi_offset r30, -16
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; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 0, 16(1)
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; CHECK-NEXT: stdu 1, -64(1)
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; CHECK-NEXT: ld 29, 0(3)
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; CHECK-NEXT: ld 30, 32(1)
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; CHECK-NEXT: cmpld 30, 29
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; CHECK-NEXT: bge- 0, .LBB0_2
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_1: # %bounds.ok
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; CHECK: lfsx 2, 0, 3
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; CHECK-NEXT: xxlxor 1, 1, 1
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; CHECK-NEXT: bl fmodf
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi 30, 30, 1
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; CHECK-NEXT: stfsx 1, 0, 3
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; CHECK-NEXT: cmpld 30, 29
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; CHECK-NEXT: blt+ 0, .LBB0_1
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; CHECK-NEXT: .LBB0_2: # %bounds.fail
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; CHECK-NEXT: std 30, 32(1)
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%pos = alloca i64, align 8
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br label %forcond
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forcond: ; preds = %bounds.ok, %0
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%1 = load i64, i64* %pos
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%.len1 = load i64, i64* undef
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%bounds.cmp = icmp ult i64 %1, %.len1
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br i1 %bounds.cmp, label %bounds.ok, label %bounds.fail
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bounds.ok: ; preds = %forcond
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%2 = load float, float* undef
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%3 = frem float 0.000000e+00, %2
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store float %3, float* undef
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%4 = load i64, i64* %pos
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%5 = add i64 %4, 1
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store i64 %5, i64* %pos
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br label %forcond
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bounds.fail: ; preds = %forcond
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unreachable
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}
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