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e349d1bd0a
To make ISD::VSELECT available(legal) so long as there are altivec instruction, otherwise it's default behavior is expanding, which is legalized at type-legalization phase. Use xxsel to match vselect if vsx is open, or use vsel. Differential Revision: https://reviews.llvm.org/D49531 llvm-svn: 346824
101 lines
3.4 KiB
LLVM
101 lines
3.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
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; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX
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; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
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; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
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entry:
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%m = fcmp oeq <4 x float> %c, %d
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%v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
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ret <4 x float> %v
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}
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; CHECK-VSX-LABLE: test1
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; CHECK-VSX: xvcmpeqsp [[REG1:(vs|v)[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, [[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test1
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; CHECK-NOVSX: vcmpeqfp v[[REG1:[0-9]+]], v4, v5
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; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
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; CHECK-NOVSX: blr
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define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
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entry:
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%m = fcmp oeq <2 x double> %c, %d
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%v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
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ret <2 x double> %v
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}
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; CHECK-VSX-LABLE: test2
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; CHECK-VSX: xvcmpeqdp [[REG1:(vs|v)[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, [[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test2
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; CHECK-NOVSX: fcmp
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; CHECK-NOVSX: fcmp
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; CHECK-NOVSX: blr
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define <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
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entry:
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%m = icmp eq <16 x i8> %c, %d
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%v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %v
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}
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; CHECK-VSX-LABLE: test3
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; CHECK-VSX: vcmpequb v[[REG1:[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test3
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; CHECK-NOVSX: vcmpequb v[[REG1:[0-9]+]], v4, v5
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; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
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; CHECK-NOVSX: blr
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define <8 x i16> @test4(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
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entry:
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%m = icmp eq <8 x i16> %c, %d
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%v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %v
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}
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; CHECK-VSX-LABLE: test4
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; CHECK-VSX: vcmpequh v[[REG1:[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test4
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; CHECK-NOVSX: vcmpequh v[[REG1:[0-9]+]], v4, v5
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; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
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; CHECK-NOVSX: blr
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define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
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entry:
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%m = icmp eq <4 x i32> %c, %d
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%v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %v
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}
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; CHECK-VSX-LABLE: test5
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; CHECK-VSX: vcmpequw v[[REG1:[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test5
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; CHECK-NOVSX: vcmpequw v[[REG1:[0-9]+]], v4, v5
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; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
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; CHECK-NOVSX: blr
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define <2 x i64> @test6(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) {
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entry:
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%m = icmp eq <2 x i64> %c, %d
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%v = select <2 x i1> %m, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %v
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}
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; CHECK-VSX-LABLE: test6
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; CHECK-VSX: vcmpequd v[[REG1:[0-9]+]], v4, v5
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; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
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; CHECK-VSX: blr
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; CHECK-NOVSX-LABLE: test6
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; CHECK-NOVSX: vcmpequd v[[REG1:[0-9]+]], v4, v5
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; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
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; CHECK-NOVSX: blr
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