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d2cf0742a4
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic is correct and preferred according the ARM documentation (A8.6.98). The former are pseudo-instructions for the latter. llvm-svn: 114221
41 lines
1.3 KiB
LLVM
41 lines
1.3 KiB
LLVM
; RUN: llc -march=arm -mattr=+v6t2 < %s | FileCheck %s
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%struct.F = type { [3 x i8], i8 }
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@X = common global %struct.F zeroinitializer, align 4 ; <%struct.F*> [#uses=1]
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define void @f1([1 x i32] %f.coerce0) nounwind {
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entry:
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; CHECK: f1
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; CHECK: mov r2, #10
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; CHECK: bfi r1, r2, #22, #4
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%0 = load i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1]
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%1 = and i32 %0, -62914561 ; <i32> [#uses=1]
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%2 = or i32 %1, 41943040 ; <i32> [#uses=1]
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store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4
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ret void
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}
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define i32 @f2(i32 %A, i32 %B) nounwind readnone optsize {
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entry:
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; CHECK: f2
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; CHECK: lsr{{.*}}#7
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; CHECK: bfi r0, r1, #7, #16
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%and = and i32 %A, -8388481 ; <i32> [#uses=1]
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%and2 = and i32 %B, 8388480 ; <i32> [#uses=1]
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%or = or i32 %and2, %and ; <i32> [#uses=1]
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ret i32 %or
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}
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define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize {
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entry:
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; CHECK: f3
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; CHECK: lsr{{.*}} #7
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; CHECK: mov r0, r1
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; CHECK: bfi r0, r2, #7, #16
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%and = and i32 %A, 8388480 ; <i32> [#uses=1]
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%and2 = and i32 %B, -8388481 ; <i32> [#uses=1]
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%or = or i32 %and2, %and ; <i32> [#uses=1]
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ret i32 %or
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}
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