mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
38e5713f51
Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
43 lines
817 B
YAML
43 lines
817 B
YAML
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
|
|
# This test ensures that the MIR parser parses basic block successors and
|
|
# probabilities correctly.
|
|
|
|
--- |
|
|
|
|
define i32 @foo(i32 %a) {
|
|
entry:
|
|
%0 = icmp sle i32 %a, 10
|
|
br i1 %0, label %less, label %exit
|
|
|
|
less:
|
|
ret i32 0
|
|
|
|
exit:
|
|
ret i32 %a
|
|
}
|
|
|
|
...
|
|
---
|
|
name: foo
|
|
body: |
|
|
; CHECK-LABEL: bb.0.entry:
|
|
; CHECK: successors: %bb.1(0x2a3d70a4), %bb.2(0x55c28f5c)
|
|
; CHECK-LABEL: bb.1.less:
|
|
bb.0.entry:
|
|
successors: %bb.1 (33), %bb.2(67)
|
|
liveins: $edi
|
|
|
|
CMP32ri8 $edi, 10, implicit-def $eflags
|
|
JCC_1 %bb.2, 15, implicit killed $eflags
|
|
|
|
bb.1.less:
|
|
$eax = MOV32r0 implicit-def dead $eflags
|
|
RETQ killed $eax
|
|
|
|
bb.2.exit:
|
|
liveins: $edi
|
|
|
|
$eax = COPY killed $edi
|
|
RETQ killed $eax
|
|
...
|