mirror of
https://github.com/RPCS3/llvm-mirror.git
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378bc328f0
be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
484 lines
17 KiB
C++
484 lines
17 KiB
C++
//===-- Mips/MipsCodeEmitter.cpp - Convert Mips Code to Machine Code ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===---------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the Mips machine instructions
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// into relocatable machine code.
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//
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//===---------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "MipsInstrInfo.h"
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#include "MipsRelocations.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#ifndef NDEBUG
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#include <iomanip>
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#endif
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using namespace llvm;
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#define DEBUG_TYPE "jit"
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STATISTIC(NumEmitted, "Number of machine instructions emitted");
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namespace {
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class MipsCodeEmitter : public MachineFunctionPass {
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MipsJITInfo *JTI;
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const MipsInstrInfo *II;
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const DataLayout *TD;
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const MipsSubtarget *Subtarget;
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TargetMachine &TM;
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JITCodeEmitter &MCE;
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const std::vector<MachineConstantPoolEntry> *MCPEs;
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const std::vector<MachineJumpTableEntry> *MJTEs;
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bool IsPIC;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineModuleInfo> ();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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static char ID;
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public:
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MipsCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
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: MachineFunctionPass(ID), JTI(nullptr), II(nullptr), TD(nullptr),
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TM(tm), MCE(mce), MCPEs(nullptr), MJTEs(nullptr),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "Mips Machine Code Emitter";
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}
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/// getBinaryCodeForInstr - This function, generated by the
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/// CodeEmitterGenerator using TableGen, produces the binary encoding for
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/// machine instructions.
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uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
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void emitInstruction(MachineBasicBlock::instr_iterator MI,
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MachineBasicBlock &MBB);
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private:
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void emitWord(unsigned Word);
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/// Routines that handle operands which add machine relocations which are
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/// fixed up by the relocation stage.
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void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
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bool MayNeedFarStub) const;
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void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
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void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
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void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
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void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const;
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unsigned getRelocation(const MachineInstr &MI,
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const MachineOperand &MO) const;
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unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getBranchTargetOpValueMM(const MachineInstr &MI,
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unsigned OpNo) const;
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unsigned getBranchTarget21OpValue(const MachineInstr &MI,
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unsigned OpNo) const;
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unsigned getBranchTarget26OpValue(const MachineInstr &MI,
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unsigned OpNo) const;
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unsigned getJumpOffset16OpValue(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMemEncodingMMImm12(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMSAMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getSimm19Lsl2Encoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getSimm18Lsl3Encoding(const MachineInstr &MI, unsigned OpNo) const;
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/// Expand pseudo instructions with accumulator register operands.
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void expandACCInstr(MachineBasicBlock::instr_iterator MI,
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MachineBasicBlock &MBB, unsigned Opc) const;
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void expandPseudoIndirectBranch(MachineBasicBlock::instr_iterator MI,
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MachineBasicBlock &MBB) const;
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/// \brief Expand pseudo instruction. Return true if MI was expanded.
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bool expandPseudos(MachineBasicBlock::instr_iterator &MI,
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MachineBasicBlock &MBB) const;
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};
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}
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char MipsCodeEmitter::ID = 0;
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bool MipsCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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MipsTargetMachine &Target = static_cast<MipsTargetMachine &>(
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const_cast<TargetMachine &>(MF.getTarget()));
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// Initialize the subtarget so that we can grab the subtarget dependent
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// variables from it.
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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JTI = Target.getSubtargetImpl()->getJITInfo();
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II = Subtarget->getInstrInfo();
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TD = Subtarget->getDataLayout();
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MCPEs = &MF.getConstantPool()->getConstants();
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MJTEs = nullptr;
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if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
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JTI->Initialize(MF, IsPIC, Subtarget->isLittle());
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MCE.setModuleInfo(&getAnalysis<MachineModuleInfo> ());
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do {
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DEBUG(errs() << "JITTing function '"
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<< MF.getName() << "'\n");
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MCE.startFunction(MF);
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB){
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MCE.StartMachineBasicBlock(MBB);
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for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(),
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E = MBB->instr_end(); I != E;)
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emitInstruction(*I++, *MBB);
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}
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} while (MCE.finishFunction(MF));
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return false;
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}
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unsigned MipsCodeEmitter::getRelocation(const MachineInstr &MI,
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const MachineOperand &MO) const {
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// NOTE: This relocations are for static.
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uint64_t TSFlags = MI.getDesc().TSFlags;
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uint64_t Form = TSFlags & MipsII::FormMask;
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if (Form == MipsII::FrmJ)
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return Mips::reloc_mips_26;
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if ((Form == MipsII::FrmI || Form == MipsII::FrmFI)
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&& MI.isBranch())
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return Mips::reloc_mips_pc16;
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if (Form == MipsII::FrmI && MI.getOpcode() == Mips::LUi)
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return Mips::reloc_mips_hi;
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return Mips::reloc_mips_lo;
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}
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unsigned MipsCodeEmitter::getJumpTargetOpValue(const MachineInstr &MI,
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unsigned OpNo) const {
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MachineOperand MO = MI.getOperand(OpNo);
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if (MO.isGlobal())
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emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO), true);
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else if (MO.isSymbol())
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emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO));
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else if (MO.isMBB())
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emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO));
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else
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llvm_unreachable("Unexpected jump target operand kind.");
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return 0;
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}
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unsigned MipsCodeEmitter::getJumpTargetOpValueMM(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getBranchTargetOpValueMM(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getBranchTarget21OpValue(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getBranchTarget26OpValue(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getJumpOffset16OpValue(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI,
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unsigned OpNo) const {
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MachineOperand MO = MI.getOperand(OpNo);
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emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO));
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return 0;
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}
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unsigned MipsCodeEmitter::getMemEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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// Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
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assert(MI.getOperand(OpNo).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16;
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return (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits;
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}
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unsigned MipsCodeEmitter::getMemEncodingMMImm12(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getMSAMemEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getSizeExtEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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// size is encoded as size-1.
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return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;
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}
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unsigned MipsCodeEmitter::getSizeInsEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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// size is encoded as pos+size-1.
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return getMachineOpValue(MI, MI.getOperand(OpNo-1)) +
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getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;
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}
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unsigned MipsCodeEmitter::getLSAImmEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getSimm18Lsl3Encoding(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getSimm19Lsl2Encoding(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const {
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if (MO.isReg())
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return TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(
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MO.getReg());
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else if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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else if (MO.isGlobal())
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emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO), true);
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else if (MO.isSymbol())
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emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO));
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else if (MO.isCPI())
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emitConstPoolAddress(MO.getIndex(), getRelocation(MI, MO));
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else if (MO.isJTI())
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emitJumpTableAddress(MO.getIndex(), getRelocation(MI, MO));
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else if (MO.isMBB())
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emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO));
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else
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llvm_unreachable("Unable to encode MachineOperand!");
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return 0;
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}
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void MipsCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
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bool MayNeedFarStub) const {
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
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const_cast<GlobalValue *>(GV), 0,
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MayNeedFarStub));
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}
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void MipsCodeEmitter::
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emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, ES, 0, 0));
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}
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void MipsCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, CPI, 0, false));
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}
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void MipsCodeEmitter::
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emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
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Reloc, JTIndex, 0, false));
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}
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void MipsCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
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unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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Reloc, BB));
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}
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void MipsCodeEmitter::emitInstruction(MachineBasicBlock::instr_iterator MI,
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MachineBasicBlock &MBB) {
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DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << *MI);
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// Expand pseudo instruction. Skip if MI was not expanded.
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if (((MI->getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo) &&
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!expandPseudos(MI, MBB))
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return;
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MCE.processDebugLoc(MI->getDebugLoc(), true);
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emitWord(getBinaryCodeForInstr(*MI));
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++NumEmitted; // Keep track of the # of mi's emitted
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MCE.processDebugLoc(MI->getDebugLoc(), false);
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}
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void MipsCodeEmitter::emitWord(unsigned Word) {
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DEBUG(errs() << " 0x";
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errs().write_hex(Word) << "\n");
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if (Subtarget->isLittle())
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MCE.emitWordLE(Word);
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else
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MCE.emitWordBE(Word);
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}
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void MipsCodeEmitter::expandACCInstr(MachineBasicBlock::instr_iterator MI,
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MachineBasicBlock &MBB,
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unsigned Opc) const {
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// Expand "pseudomult $ac0, $t0, $t1" to "mult $t0, $t1".
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BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Opc))
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.addReg(MI->getOperand(1).getReg()).addReg(MI->getOperand(2).getReg());
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}
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void MipsCodeEmitter::expandPseudoIndirectBranch(
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MachineBasicBlock::instr_iterator MI, MachineBasicBlock &MBB) const {
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// This logic is duplicated from MipsAsmPrinter::emitPseudoIndirectBranch()
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bool HasLinkReg = false;
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unsigned Opcode = 0;
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if (Subtarget->hasMips64r6()) {
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// MIPS64r6 should use (JALR64 ZERO_64, $rs)
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Opcode = Mips::JALR64;
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HasLinkReg = true;
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} else if (Subtarget->hasMips32r6()) {
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// MIPS32r6 should use (JALR ZERO, $rs)
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Opcode = Mips::JALR;
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HasLinkReg = true;
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} else if (Subtarget->inMicroMipsMode())
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// microMIPS should use (JR_MM $rs)
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Opcode = Mips::JR_MM;
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else {
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// Everything else should use (JR $rs)
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Opcode = Mips::JR;
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}
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auto MIB = BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Opcode));
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if (HasLinkReg) {
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unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
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MIB.addReg(ZeroReg);
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}
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MIB.addReg(MI->getOperand(0).getReg());
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}
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bool MipsCodeEmitter::expandPseudos(MachineBasicBlock::instr_iterator &MI,
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MachineBasicBlock &MBB) const {
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switch (MI->getOpcode()) {
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default:
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llvm_unreachable("Unhandled pseudo");
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return false;
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case Mips::NOP:
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BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO)
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.addReg(Mips::ZERO).addImm(0);
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break;
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case Mips::B:
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BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::BEQ)).addReg(Mips::ZERO)
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.addReg(Mips::ZERO).addOperand(MI->getOperand(0));
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break;
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case Mips::TRAP:
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BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::BREAK)).addImm(0)
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.addImm(0);
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break;
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case Mips::JALRPseudo:
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BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::JALR), Mips::RA)
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.addReg(MI->getOperand(0).getReg());
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break;
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case Mips::PseudoMULT:
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expandACCInstr(MI, MBB, Mips::MULT);
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break;
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case Mips::PseudoMULTu:
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expandACCInstr(MI, MBB, Mips::MULTu);
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break;
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case Mips::PseudoSDIV:
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expandACCInstr(MI, MBB, Mips::SDIV);
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break;
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case Mips::PseudoUDIV:
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expandACCInstr(MI, MBB, Mips::UDIV);
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break;
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case Mips::PseudoMADD:
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expandACCInstr(MI, MBB, Mips::MADD);
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break;
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case Mips::PseudoMADDU:
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expandACCInstr(MI, MBB, Mips::MADDU);
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break;
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case Mips::PseudoMSUB:
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expandACCInstr(MI, MBB, Mips::MSUB);
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break;
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case Mips::PseudoMSUBU:
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expandACCInstr(MI, MBB, Mips::MSUBU);
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break;
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case Mips::PseudoReturn:
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case Mips::PseudoReturn64:
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case Mips::PseudoIndirectBranch:
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case Mips::PseudoIndirectBranch64:
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expandPseudoIndirectBranch(MI, MBB);
|
|
break;
|
|
case TargetOpcode::CFI_INSTRUCTION:
|
|
case TargetOpcode::IMPLICIT_DEF:
|
|
case TargetOpcode::KILL:
|
|
// Do nothing
|
|
return false;
|
|
}
|
|
|
|
(MI--)->eraseFromBundle();
|
|
return true;
|
|
}
|
|
|
|
/// createMipsJITCodeEmitterPass - Return a pass that emits the collected Mips
|
|
/// code to the specified MCE object.
|
|
FunctionPass *llvm::createMipsJITCodeEmitterPass(MipsTargetMachine &TM,
|
|
JITCodeEmitter &JCE) {
|
|
return new MipsCodeEmitter(TM, JCE);
|
|
}
|
|
|
|
#include "MipsGenCodeEmitter.inc"
|