Andrey Turetskiy 79cd7e75f9 [X86] Restrict max long nop length for Lakemont. ... Restrict the max length of long nops for Lakemont to 7. Experiments on MCU benchmarks (Dhrystone, Coremark) show that this is the most optimal length. Differential Revision: http://reviews.llvm.org/D18897 llvm-svn: 265924		2016-04-11 10:07:36 +00:00
..
AArch64	AArch64: support .cpu directive	2016-04-02 19:29:52 +00:00
AMDGPU	[AMDGPU] AsmParser: disable DPP for unsupported instructions. New dpp tests. Fix v_nop_dpp.	2016-04-06 13:29:59 +00:00
ARM	Revert r265817	2016-04-08 18:15:37 +00:00
AsmParser
COFF
Disassembler	[mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* instructions	2016-04-08 07:27:26 +00:00
ELF	[MC] support TLSDESC and TLSCALL / GNU2 tls dialect	2016-04-09 20:32:33 +00:00
Hexagon	Revert r265817	2016-04-08 18:15:37 +00:00
Lanai	[lanai] isBrImm should accept any non-constant immediate.	2016-03-31 17:58:55 +00:00
MachO	Add missing emissionKind flags to the DICompileUnits of several old testcases.	2016-04-01 22:18:43 +00:00
Markup
Mips	Revert r265817	2016-04-08 18:15:37 +00:00
PowerPC	[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance	2016-04-06 01:47:02 +00:00
Sparc
SystemZ	[SystemZ] Add compare-and-branch instructions to MC	2016-04-04 14:26:43 +00:00
X86	[X86] Restrict max long nop length for Lakemont.	2016-04-11 10:07:36 +00:00