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861e8a0eb7
llvm-mirror/test
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Lei Huang 861e8a0eb7 [PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX 
The match pattern in the definition of LXSDX is xoaddr, so the Pseudo
instruction XFLOADf64 never gets selected. XFLOADf64 expands to LXSDX/LFDX post
RA based on the register pressure. To avoid ambiguity, we need to remove the
select pattern for LXSDX, same as what was done for LXSD. STXSDX also have
the same issue.

Patch by Qing Shan Zhang (steven.zhang).

Differential Revision: https://reviews.llvm.org/D47178

llvm-svn: 333150
2018-05-24 03:20:28 +00:00
..
Analysis Fix aliasing of launder.invariant.group 2018-05-23 09:16:44 +00:00
Assembler [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
Bindings [LLVM-C] Add DIBuilder Bindings For ObjC Classes 2018-05-21 16:27:35 +00:00
Bitcode [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
BugPoint
CodeGen [PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX 2018-05-24 03:20:28 +00:00
DebugInfo Move a debug info test into the X86 directory 2018-05-23 22:50:45 +00:00
Examples
ExecutionEngine [RuntimeDyld][MachO] Add support for MachO::ARM64_RELOC_POINTER_TO_GOT reloc. 2018-05-23 21:27:07 +00:00
Feature
FileCheck
Instrumentation [msan] Don't check divisor shadow in fdiv. 2018-05-18 20:19:53 +00:00
Integer
JitListener [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
Linker [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
LTO [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
MC [RISCV] Add symbol diff relocation support for RISC-V 2018-05-23 12:36:18 +00:00
Object [WebAsembly] Update default triple in test files to wasm32-unknown-unkown. 2018-05-10 17:49:11 +00:00
ObjectYAML Resubmit [pdb] Change /DEBUG:GHASH to emit 8 byte hashes." 2018-05-17 22:55:15 +00:00
Other Add remarks describing when a pass changes the IR instruction count of a module 2018-05-18 17:26:39 +00:00
SafepointIRVerifier SafepointIRVerifier is made unreachable block tolerant 2018-05-23 05:54:55 +00:00
SymbolRewriter
TableGen [GlobalISel][InstructionSelect] Moving Reg Bank Checks forward, perf patch 9 2018-05-23 23:58:10 +00:00
ThinLTO/X86 [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
tools [llvm-strip] Minor fix of the usage of TableGen 2018-05-23 20:39:52 +00:00
Transforms StructurizeCFG: Adjust the loop depth for a subregion to order the nodes correctly 2018-05-23 18:34:48 +00:00
Unit
Verifier [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
YAMLParser
.clang-format
CMakeLists.txt [tools] Add missing test dependency 2018-05-07 22:00:59 +00:00
lit.cfg.py [tools] Adjust the lit config for llvm-strip 2018-05-07 21:07:01 +00:00
lit.site.cfg.py.in Remove 'abi-breaking-checks' lit feature. 2018-05-09 12:39:39 +00:00
TestRunner.sh