Simon Pilgrim af199cc3ef [TargetLowering] Improve expandFunnelShift shift amount masking ... For the 'inverse shift', we currently always perform a subtraction of the original (masked) shift amount. But for the case where we are handling power-of-2 type widths, we can replace: (sub bw-1, (and amt, bw-1) ) -> (and (xor amt, bw-1), bw-1) -> (and ~amt, bw-1) This allows x86 shifts to fold away the and-mask. Followup to D77301 + D80466. http://volta.cs.utah.edu:8080/z/Nod0Gr Differential Revision: https://reviews.llvm.org/D80489		2020-05-24 11:25:09 +01:00
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Analysis	[SCEV] Constant fold MultExpr before applying depth limit.	2020-05-22 18:34:32 +03:00
Assembler
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CodeGen	[TargetLowering] Improve expandFunnelShift shift amount masking	2020-05-24 11:25:09 +01:00
DebugInfo	Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"	2020-05-22 05:36:15 -06:00
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ExecutionEngine	[JITLink] Initial implementation of ELF / x86-64 support for JITLink.	2020-05-21 21:44:00 -07:00
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FileCheck	Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"	2020-05-22 05:36:15 -06:00
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MC	[PowerPC] Add support for vmsumudm	2020-05-22 14:35:13 -05:00
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Other	[VectorCombine] set preserve alias analysis	2020-05-22 16:25:16 -04:00
Reduce
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ThinLTO/X86
tools	[yaml2obj] - Add a technical prefix for each unnamed chunk.	2020-05-23 17:22:23 +03:00
Transforms	AMDGPU: Refine rcp/rsq intrinsic folding for modern FP rules	2020-05-23 13:28:36 -04:00
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