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dd9041a377
The irony of this patch is that one CPU that is affected is AMD Jaguar, and Jaguar has a completely double-pumped AVX implementation. But getting the cost model to reflect that is a much bigger problem. The small goal here is simply to improve on the lie that !AVX2 == SandyBridge. Differential Revision: http://reviews.llvm.org/D18000 llvm-svn: 263069
53 lines
2.1 KiB
LLVM
53 lines
2.1 KiB
LLVM
; RUN: opt < %s -loop-vectorize -mattr=avx,+slow-unaligned-mem-32 -S | FileCheck %s --check-prefix=SLOWMEM32 --check-prefix=CHECK
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; RUN: opt < %s -loop-vectorize -mattr=avx,-slow-unaligned-mem-32 -S | FileCheck %s --check-prefix=FASTMEM32 --check-prefix=CHECK
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.8.0"
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; CHECK-LABEL: @read_mod_write_single_ptr(
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; CHECK: load <8 x float>
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; CHECK: ret i32
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define i32 @read_mod_write_single_ptr(float* nocapture %a, i32 %n) nounwind uwtable ssp {
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%1 = icmp sgt i32 %n, 0
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br i1 %1, label %.lr.ph, label %._crit_edge
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.lr.ph: ; preds = %0, %.lr.ph
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%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
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%2 = getelementptr inbounds float, float* %a, i64 %indvars.iv
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%3 = load float, float* %2, align 4
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%4 = fmul float %3, 3.000000e+00
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store float %4, float* %2, align 4
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %._crit_edge, label %.lr.ph
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._crit_edge: ; preds = %.lr.ph, %0
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ret i32 undef
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}
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; CHECK-LABEL: @read_mod_i64(
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; SLOWMEM32: load <2 x i64>
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; FASTMEM32: load <4 x i64>
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; CHECK: ret i32
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define i32 @read_mod_i64(i64* nocapture %a, i32 %n) nounwind uwtable ssp {
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%1 = icmp sgt i32 %n, 0
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br i1 %1, label %.lr.ph, label %._crit_edge
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.lr.ph: ; preds = %0, %.lr.ph
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%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
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%2 = getelementptr inbounds i64, i64* %a, i64 %indvars.iv
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%3 = load i64, i64* %2, align 4
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%4 = add i64 %3, 3
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store i64 %4, i64* %2, align 4
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %._crit_edge, label %.lr.ph
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._crit_edge: ; preds = %.lr.ph, %0
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ret i32 undef
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}
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