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863e4dd199
We removed UseVSXReg flag in https://reviews.llvm.org/D58685 But we did not reclain the bit 6 it was assigned, this will become confusing and a hole later.. We should reclaim it as early as possible before new bits. Reviewed By: sfertile Differential Revision: https://reviews.llvm.org/D72649
509 lines
22 KiB
C++
509 lines
22 KiB
C++
//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
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#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
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#include "PPCRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "PPCGenInstrInfo.inc"
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namespace llvm {
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/// PPCII - This namespace holds all of the PowerPC target-specific
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/// per-instruction flags. These must match the corresponding definitions in
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/// PPC.td and PPCInstrFormats.td.
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namespace PPCII {
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enum {
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// PPC970 Instruction Flags. These flags describe the characteristics of the
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// PowerPC 970 (aka G5) dispatch groups and how they are formed out of
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// raw machine instructions.
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/// PPC970_First - This instruction starts a new dispatch group, so it will
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/// always be the first one in the group.
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PPC970_First = 0x1,
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/// PPC970_Single - This instruction starts a new dispatch group and
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/// terminates it, so it will be the sole instruction in the group.
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PPC970_Single = 0x2,
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/// PPC970_Cracked - This instruction is cracked into two pieces, requiring
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/// two dispatch pipes to be available to issue.
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PPC970_Cracked = 0x4,
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/// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
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/// an instruction is issued to.
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PPC970_Shift = 3,
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PPC970_Mask = 0x07 << PPC970_Shift
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};
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enum PPC970_Unit {
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/// These are the various PPC970 execution unit pipelines. Each instruction
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/// is one of these.
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PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
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PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
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PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
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PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
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PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
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PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
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PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
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PPC970_BRU = 7 << PPC970_Shift // Branch Unit
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};
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enum {
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/// Shift count to bypass PPC970 flags
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NewDef_Shift = 6,
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/// This instruction is an X-Form memory operation.
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XFormMemOp = 0x1 << NewDef_Shift
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};
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} // end namespace PPCII
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// Instructions that have an immediate form might be convertible to that
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// form if the correct input is a result of a load immediate. In order to
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// know whether the transformation is special, we might need to know some
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// of the details of the two forms.
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struct ImmInstrInfo {
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// Is the immediate field in the immediate form signed or unsigned?
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uint64_t SignedImm : 1;
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// Does the immediate need to be a multiple of some value?
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uint64_t ImmMustBeMultipleOf : 5;
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// Is R0/X0 treated specially by the original r+r instruction?
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// If so, in which operand?
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uint64_t ZeroIsSpecialOrig : 3;
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// Is R0/X0 treated specially by the new r+i instruction?
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// If so, in which operand?
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uint64_t ZeroIsSpecialNew : 3;
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// Is the operation commutative?
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uint64_t IsCommutative : 1;
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// The operand number to check for add-immediate def.
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uint64_t OpNoForForwarding : 3;
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// The operand number for the immediate.
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uint64_t ImmOpNo : 3;
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// The opcode of the new instruction.
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uint64_t ImmOpcode : 16;
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// The size of the immediate.
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uint64_t ImmWidth : 5;
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// The immediate should be truncated to N bits.
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uint64_t TruncateImmTo : 5;
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// Is the instruction summing the operand
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uint64_t IsSummingOperands : 1;
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};
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// Information required to convert an instruction to just a materialized
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// immediate.
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struct LoadImmediateInfo {
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unsigned Imm : 16;
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unsigned Is64Bit : 1;
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unsigned SetCR : 1;
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};
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class PPCSubtarget;
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class PPCInstrInfo : public PPCGenInstrInfo {
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PPCSubtarget &Subtarget;
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const PPCRegisterInfo RI;
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void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
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int FrameIdx, const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr *> &NewMIs) const;
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void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr *> &NewMIs) const;
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// If the inst has imm-form and one of its operand is produced by a LI,
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// put the imm into the inst directly and remove the LI if possible.
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bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
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unsigned ConstantOpNo, MachineInstr &DefMI,
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int64_t Imm) const;
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// If the inst has imm-form and one of its operand is produced by an
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// add-immediate, try to transform it when possible.
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bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
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unsigned ConstantOpNo, MachineInstr &DefMI,
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bool KillDefMI) const;
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// Try to find that, if the instruction 'MI' contains any operand that
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// could be forwarded from some inst that feeds it. If yes, return the
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// Def of that operand. And OpNoForForwarding is the operand index in
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// the 'MI' for that 'Def'. If we see another use of this Def between
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// the Def and the MI, SeenIntermediateUse becomes 'true'.
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MachineInstr *getForwardingDefMI(MachineInstr &MI,
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unsigned &OpNoForForwarding,
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bool &SeenIntermediateUse) const;
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// Can the user MI have it's source at index \p OpNoForForwarding
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// forwarded from an add-immediate that feeds it?
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bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
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unsigned OpNoForForwarding) const;
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bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
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const ImmInstrInfo &III,
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MachineOperand *&ImmMO,
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MachineOperand *&RegMO) const;
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bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
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const MachineInstr &DefMI,
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const ImmInstrInfo &III,
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int64_t &Imm) const;
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bool isRegElgibleForForwarding(const MachineOperand &RegMO,
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const MachineInstr &DefMI,
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const MachineInstr &MI, bool KillDefMI,
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bool &IsFwdFeederRegKilled) const;
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const unsigned *getStoreOpcodesForSpillArray() const;
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const unsigned *getLoadOpcodesForSpillArray() const;
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virtual void anchor();
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protected:
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/// Commutes the operands in the given instruction.
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/// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
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///
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/// Do not call this method for a non-commutable instruction or for
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/// non-commutable pair of operand indices OpIdx1 and OpIdx2.
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/// Even though the instruction is commutable, the method may still
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/// fail to commute the operands, null pointer is returned in such cases.
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///
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/// For example, we can commute rlwimi instructions, but only if the
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/// rotate amt is zero. We also have to munge the immediates a bit.
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const override;
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public:
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explicit PPCInstrInfo(PPCSubtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const PPCRegisterInfo &getRegisterInfo() const { return RI; }
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bool isXFormMemOp(unsigned Opcode) const {
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return get(Opcode).TSFlags & PPCII::XFormMemOp;
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}
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static bool isSameClassPhysRegCopy(unsigned Opcode) {
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unsigned CopyOpcodes[] =
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{ PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf,
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PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb,
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PPC::CROR, PPC::EVOR, -1U };
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for (int i = 0; CopyOpcodes[i] != -1U; i++)
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if (Opcode == CopyOpcodes[i])
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return true;
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return false;
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}
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ScheduleHazardRecognizer *
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CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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const ScheduleDAG *DAG) const override;
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ScheduleHazardRecognizer *
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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const ScheduleDAG *DAG) const override;
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unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr &MI,
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unsigned *PredCost = nullptr) const override;
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr &DefMI, unsigned DefIdx,
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const MachineInstr &UseMI,
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unsigned UseIdx) const override;
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int getOperandLatency(const InstrItineraryData *ItinData,
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const override {
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return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
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UseNode, UseIdx);
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}
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bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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const MachineInstr &DefMI,
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unsigned DefIdx) const override {
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// Machine LICM should hoist all instructions in low-register-pressure
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// situations; none are sufficiently free to justify leaving in a loop
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// body.
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return false;
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}
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bool useMachineCombiner() const override {
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return true;
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}
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/// Return true when there is potentially a faster code sequence
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/// for an instruction chain ending in <Root>. All potential patterns are
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/// output in the <Pattern> array.
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bool getMachineCombinerPatterns(
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MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern> &P) const override;
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bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
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bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const override;
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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AAResults *AA) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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// Branch analysis.
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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// Select analysis.
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bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
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unsigned, unsigned, int &, int &, int &) const override;
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void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, unsigned DstReg,
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ArrayRef<MachineOperand> Cond, unsigned TrueReg,
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unsigned FalseReg) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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unsigned getStoreOpcodeForSpill(unsigned Reg,
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const TargetRegisterClass *RC = nullptr) const;
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unsigned getLoadOpcodeForSpill(unsigned Reg,
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const TargetRegisterClass *RC = nullptr) const;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
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MachineRegisterInfo *MRI) const override;
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// If conversion by predication (only supported by some branch instructions).
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// All of the profitability checks always return true; it is always
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// profitable to use the predicated branches.
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bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles, unsigned ExtraPredCycles,
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BranchProbability Probability) const override {
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return true;
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}
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumT, unsigned ExtraT,
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MachineBasicBlock &FMBB,
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unsigned NumF, unsigned ExtraF,
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BranchProbability Probability) const override;
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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BranchProbability Probability) const override {
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return true;
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}
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bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const override {
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return false;
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}
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// Predication support.
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bool isPredicated(const MachineInstr &MI) const override;
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bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
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bool PredicateInstruction(MachineInstr &MI,
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ArrayRef<MachineOperand> Pred) const override;
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bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const override;
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bool DefinesPredicate(MachineInstr &MI,
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std::vector<MachineOperand> &Pred) const override;
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// Comparison optimization.
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bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &Mask, int &Value) const override;
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bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int Mask, int Value,
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const MachineRegisterInfo *MRI) const override;
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/// Return true if get the base operand, byte offset of an instruction and
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/// the memory width. Width is the size of memory that is being
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/// loaded/stored (e.g. 1, 2, 4, 8).
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bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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const MachineOperand *&BaseOp,
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int64_t &Offset, unsigned &Width,
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const TargetRegisterInfo *TRI) const;
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/// Return true if two MIs access different memory addresses and false
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/// otherwise
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bool
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areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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const MachineInstr &MIb) const override;
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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///
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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void getNoop(MCInst &NopInst) const override;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableBitmaskMachineOperandTargetFlags() const override;
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// Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
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bool expandVSXMemPseudo(MachineInstr &MI) const;
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// Lower pseudo instructions after register allocation.
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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static bool isVFRegister(unsigned Reg) {
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return Reg >= PPC::VF0 && Reg <= PPC::VF31;
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}
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static bool isVRRegister(unsigned Reg) {
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return Reg >= PPC::V0 && Reg <= PPC::V31;
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}
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const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
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static int getRecordFormOpcode(unsigned Opcode);
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bool isTOCSaveMI(const MachineInstr &MI) const;
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bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
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const unsigned PhiDepth) const;
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/// Return true if the output of the instruction is always a sign-extended,
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/// i.e. 0 to 31-th bits are same as 32-th bit.
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bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
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return isSignOrZeroExtended(MI, true, depth);
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}
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/// Return true if the output of the instruction is always zero-extended,
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/// i.e. 0 to 31-th bits are all zeros
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bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
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return isSignOrZeroExtended(MI, false, depth);
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}
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bool convertToImmediateForm(MachineInstr &MI,
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MachineInstr **KilledDef = nullptr) const;
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bool foldFrameOffset(MachineInstr &MI) const;
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bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
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bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
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bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
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unsigned &XFormOpcode,
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int64_t &OffsetOfImmInstr,
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ImmInstrInfo &III) const;
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bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
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MachineInstr *&ADDIMI, int64_t &OffsetAddi,
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int64_t OffsetImm) const;
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/// Fixup killed/dead flag for register \p RegNo between instructions [\p
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/// StartMI, \p EndMI]. Some PostRA transformations may violate register
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/// killed/dead flags semantics, this function can be called to fix up. Before
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/// calling this function,
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/// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
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/// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
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/// and possible definition for \p RegNo is \p StartMI or \p EndMI.
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/// 3. Ensure that all instructions between [\p StartMI, \p EndMI] are in same
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/// basic block.
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void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,
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unsigned RegNo) const;
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void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
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void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
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int64_t Imm) const;
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bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
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bool PostRA) const;
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// In PostRA phase, try to find instruction defines \p Reg before \p MI.
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// \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
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MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI,
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bool &SeenIntermediateUse) const;
|
|
|
|
/// getRegNumForOperand - some operands use different numbering schemes
|
|
/// for the same registers. For example, a VSX instruction may have any of
|
|
/// vs0-vs63 allocated whereas an Altivec instruction could only have
|
|
/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
|
|
/// register number needed for the opcode/operand number combination.
|
|
/// The operand number argument will be useful when we need to extend this
|
|
/// to instructions that use both Altivec and VSX numbering (for different
|
|
/// operands).
|
|
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
|
|
unsigned OpNo) {
|
|
int16_t regClass = Desc.OpInfo[OpNo].RegClass;
|
|
switch (regClass) {
|
|
// We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
|
|
// VSX32-VSX63 during encoding/disassembling
|
|
case PPC::VSSRCRegClassID:
|
|
case PPC::VSFRCRegClassID:
|
|
if (isVFRegister(Reg))
|
|
return PPC::VSX32 + (Reg - PPC::VF0);
|
|
break;
|
|
// We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
|
|
// VSX32-VSX63 during encoding/disassembling
|
|
case PPC::VSRCRegClassID:
|
|
if (isVRRegister(Reg))
|
|
return PPC::VSX32 + (Reg - PPC::V0);
|
|
break;
|
|
// Other RegClass doesn't need mapping
|
|
default:
|
|
break;
|
|
}
|
|
return Reg;
|
|
}
|
|
|
|
/// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
|
|
bool isBDNZ(unsigned Opcode) const;
|
|
|
|
/// Find the hardware loop instruction used to set-up the specified loop.
|
|
/// On PPC, we have two instructions used to set-up the hardware loop
|
|
/// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
|
|
/// instructions to indicate the end of a loop.
|
|
MachineInstr *
|
|
findLoopInstr(MachineBasicBlock &PreHeader,
|
|
SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
|
|
|
|
/// Analyze loop L, which must be a single-basic-block loop, and if the
|
|
/// conditions can be understood enough produce a PipelinerLoopInfo object.
|
|
std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
|
|
analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
|
|
};
|
|
|
|
}
|
|
|
|
#endif
|