Huihui Zhang 864c46a52c [AArch64][SVE] Allow vector of pointers as legal type for masked load/store. ... Refer to LangRef http://llvm.org/docs/LangRef.html#llvm-masked-load-intrinsics 'llvm.masked.load/store.*’ intrinsics are overloaded intrinsic, which allow the load/store data to be a vector of any integer, floating-point or pointer data type. Therefore, allow pointer data type when checking 'isLegalMaskedLoadStore()'. Reviewed By: paulwalker-arm Differential Revision: https://reviews.llvm.org/D85045		2020-07-31 17:30:23 -07:00
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AArch64	[AArch64][SVE] Allow vector of pointers as legal type for masked load/store.	2020-07-31 17:30:23 -07:00
AMDGPU	Support addrspacecast initializers with isNoopAddrSpaceCast	2020-07-31 10:42:43 -04:00
ARC
ARM	[MachineCopyPropagation] BackwardPropagatableCopy: add check for hasOverlappingMultipleDef	2020-07-29 16:21:01 +01:00
AVR
BPF
Generic
Hexagon	Align store conditional address	2020-07-30 10:42:00 -05:00
Inputs
Lanai
Mips
MIR	AMDGPU: Serialize MFI spill fields	2020-07-28 20:01:57 -04:00
MSP430
NVPTX
PowerPC	[PowerPC] Retrieve the offset from load/store if it stores to stack slots	2020-07-31 07:08:20 +00:00
RISCV
SPARC
SystemZ
Thumb
Thumb2	[DAGCombiner] Fold sext_inreg of a masked load into a sign extended masked load	2020-07-30 10:34:02 +01:00
VE
WebAssembly	[WebAssembly] Fixed 64-bit indices in br_table	2020-07-30 10:52:16 -07:00
WinCFGuard
WinEH
X86	Rename basic block sections options to be consistent.	2020-07-31 11:50:55 -07:00
XCore