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8696a6109b
This iterator class provides a more abstract interface to the (Idx, Mask) lists of super-registers for a register class. The layout of the tables shouldn't be exposed to clients. llvm-svn: 156144
176 lines
6.1 KiB
C++
176 lines
6.1 KiB
C++
//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetRegisterInfo interface.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
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regclass_iterator RCB, regclass_iterator RCE,
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const char *const *subregindexnames)
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: InfoDesc(ID), SubRegIndexNames(subregindexnames),
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RegClassBegin(RCB), RegClassEnd(RCE) {
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}
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TargetRegisterInfo::~TargetRegisterInfo() {}
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void PrintReg::print(raw_ostream &OS) const {
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if (!Reg)
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OS << "%noreg";
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else if (TargetRegisterInfo::isStackSlot(Reg))
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OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
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else if (TargetRegisterInfo::isVirtualRegister(Reg))
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OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
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else if (TRI && Reg < TRI->getNumRegs())
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OS << '%' << TRI->getName(Reg);
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else
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OS << "%physreg" << Reg;
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if (SubIdx) {
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if (TRI)
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OS << ':' << TRI->getSubRegIndexName(SubIdx);
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else
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OS << ":sub(" << SubIdx << ')';
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}
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}
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/// getAllocatableClass - Return the maximal subclass of the given register
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/// class that is alloctable, or NULL.
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const TargetRegisterClass *
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TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
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if (!RC || RC->isAllocatable())
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return RC;
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const unsigned *SubClass = RC->getSubClassMask();
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for (unsigned Base = 0, BaseE = getNumRegClasses();
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Base < BaseE; Base += 32) {
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unsigned Idx = Base;
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for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
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unsigned Offset = CountTrailingZeros_32(Mask);
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const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
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if (SubRC->isAllocatable())
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return SubRC;
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Mask >>= Offset;
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Idx += Offset + 1;
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}
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}
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return NULL;
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}
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/// getMinimalPhysRegClass - Returns the Register Class of a physical
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/// register of the given type, picking the most sub register class of
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/// the right type that contains this physreg.
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const TargetRegisterClass *
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TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
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assert(isPhysicalRegister(reg) && "reg must be a physical register");
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// Pick the most sub register class of the right type that contains
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// this physreg.
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const TargetRegisterClass* BestRC = 0;
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for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
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const TargetRegisterClass* RC = *I;
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if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
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(!BestRC || BestRC->hasSubClass(RC)))
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BestRC = RC;
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}
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assert(BestRC && "Couldn't find the register class");
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return BestRC;
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}
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/// getAllocatableSetForRC - Toggle the bits that represent allocatable
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/// registers for the specific register class.
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static void getAllocatableSetForRC(const MachineFunction &MF,
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const TargetRegisterClass *RC, BitVector &R){
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assert(RC->isAllocatable() && "invalid for nonallocatable sets");
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ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
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for (unsigned i = 0; i != Order.size(); ++i)
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R.set(Order[i]);
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}
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BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
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const TargetRegisterClass *RC) const {
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BitVector Allocatable(getNumRegs());
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if (RC) {
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// A register class with no allocatable subclass returns an empty set.
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const TargetRegisterClass *SubClass = getAllocatableClass(RC);
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if (SubClass)
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getAllocatableSetForRC(MF, SubClass, Allocatable);
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} else {
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for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
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E = regclass_end(); I != E; ++I)
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if ((*I)->isAllocatable())
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getAllocatableSetForRC(MF, *I, Allocatable);
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}
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// Mask out the reserved registers
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BitVector Reserved = getReservedRegs(MF);
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Allocatable &= Reserved.flip();
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return Allocatable;
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}
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const TargetRegisterClass *
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TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B) const {
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// First take care of the trivial cases.
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if (A == B)
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return A;
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if (!A || !B)
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return 0;
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// Register classes are ordered topologically, so the largest common
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// sub-class it the common sub-class with the smallest ID.
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const unsigned *SubA = A->getSubClassMask();
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const unsigned *SubB = B->getSubClassMask();
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// We could start the search from max(A.ID, B.ID), but we are only going to
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// execute 2-3 iterations anyway.
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for (unsigned Base = 0, BaseE = getNumRegClasses(); Base < BaseE; Base += 32)
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if (unsigned Common = *SubA++ & *SubB++)
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return getRegClass(Base + CountTrailingZeros_32(Common));
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// No common sub-class exists.
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return NULL;
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}
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const TargetRegisterClass *
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TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned Idx) const {
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assert(A && B && "Missing register class");
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assert(Idx && "Bad sub-register index");
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// Find Idx in the list of super-register indices.
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const uint32_t *Mask = 0;
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for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
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if (RCI.getSubReg() == Idx) {
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Mask = RCI.getMask();
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break;
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}
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if (!Mask)
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return 0;
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// The bit mask contains all register classes that are projected into B by
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// Idx. Find a class that is also a sub-class of A.
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const uint32_t *SC = A->getSubClassMask();
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// Find the first common register class in TV and SC.
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for (unsigned Base = 0, BaseE = getNumRegClasses(); Base < BaseE; Base += 32)
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if (unsigned Common = *Mask++ & *SC++)
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return getRegClass(Base + CountTrailingZeros_32(Common));
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return 0;
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}
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