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https://github.com/RPCS3/llvm-mirror.git
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6d33546b4a
Adds a comment to the start of each test summarizing the area the test covers. llvm-svn: 189465
206 lines
8.0 KiB
LLVM
206 lines
8.0 KiB
LLVM
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
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; use the result as a third operand and perform fixed-point operations.
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; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
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@llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_madd_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16
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@llvm_mips_madd_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_madd_q_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_madd_q_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_madd_q_h_ARG2
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%2 = load <8 x i16>* @llvm_mips_madd_q_h_ARG3
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%3 = tail call <8 x i16> @llvm.mips.madd.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
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store <8 x i16> %3, <8 x i16>* @llvm_mips_madd_q_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.madd.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
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; CHECK: llvm_mips_madd_q_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: madd_q.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_madd_q_h_test
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;
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@llvm_mips_madd_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_madd_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_madd_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16
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@llvm_mips_madd_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_madd_q_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_madd_q_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_madd_q_w_ARG2
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%2 = load <4 x i32>* @llvm_mips_madd_q_w_ARG3
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%3 = tail call <4 x i32> @llvm.mips.madd.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
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store <4 x i32> %3, <4 x i32>* @llvm_mips_madd_q_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.madd.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
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; CHECK: llvm_mips_madd_q_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: madd_q.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_madd_q_w_test
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;
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@llvm_mips_maddr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_maddr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_maddr_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16
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@llvm_mips_maddr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_maddr_q_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_maddr_q_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_maddr_q_h_ARG2
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%2 = load <8 x i16>* @llvm_mips_maddr_q_h_ARG3
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%3 = tail call <8 x i16> @llvm.mips.maddr.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
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store <8 x i16> %3, <8 x i16>* @llvm_mips_maddr_q_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.maddr.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
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; CHECK: llvm_mips_maddr_q_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: maddr_q.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_maddr_q_h_test
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;
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@llvm_mips_maddr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_maddr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_maddr_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16
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@llvm_mips_maddr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_maddr_q_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_maddr_q_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_maddr_q_w_ARG2
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%2 = load <4 x i32>* @llvm_mips_maddr_q_w_ARG3
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%3 = tail call <4 x i32> @llvm.mips.maddr.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
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store <4 x i32> %3, <4 x i32>* @llvm_mips_maddr_q_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.maddr.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
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; CHECK: llvm_mips_maddr_q_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: maddr_q.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_maddr_q_w_test
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;
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@llvm_mips_msub_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_msub_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_msub_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16
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@llvm_mips_msub_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_msub_q_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_msub_q_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_msub_q_h_ARG2
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%2 = load <8 x i16>* @llvm_mips_msub_q_h_ARG3
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%3 = tail call <8 x i16> @llvm.mips.msub.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
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store <8 x i16> %3, <8 x i16>* @llvm_mips_msub_q_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.msub.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
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; CHECK: llvm_mips_msub_q_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: msub_q.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_msub_q_h_test
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;
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@llvm_mips_msub_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_msub_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_msub_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16
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@llvm_mips_msub_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_msub_q_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_msub_q_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_msub_q_w_ARG2
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%2 = load <4 x i32>* @llvm_mips_msub_q_w_ARG3
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%3 = tail call <4 x i32> @llvm.mips.msub.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
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store <4 x i32> %3, <4 x i32>* @llvm_mips_msub_q_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.msub.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
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; CHECK: llvm_mips_msub_q_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: msub_q.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_msub_q_w_test
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;
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@llvm_mips_msubr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_msubr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_msubr_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16
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@llvm_mips_msubr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_msubr_q_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_msubr_q_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_msubr_q_h_ARG2
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%2 = load <8 x i16>* @llvm_mips_msubr_q_h_ARG3
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%3 = tail call <8 x i16> @llvm.mips.msubr.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
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store <8 x i16> %3, <8 x i16>* @llvm_mips_msubr_q_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.msubr.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
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; CHECK: llvm_mips_msubr_q_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: msubr_q.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_msubr_q_h_test
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;
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@llvm_mips_msubr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_msubr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_msubr_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16
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@llvm_mips_msubr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_msubr_q_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_msubr_q_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_msubr_q_w_ARG2
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%2 = load <4 x i32>* @llvm_mips_msubr_q_w_ARG3
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%3 = tail call <4 x i32> @llvm.mips.msubr.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
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store <4 x i32> %3, <4 x i32>* @llvm_mips_msubr_q_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.msubr.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
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; CHECK: llvm_mips_msubr_q_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: msubr_q.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_msubr_q_w_test
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;
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