mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 20:12:56 +02:00
de92dc3fe2
Add an option to enable the analysis of MachineFunction register usage to extract the list of clobbered registers. When enabled, the CodeGen order is changed to be bottom up on the Call Graph. The analysis is split in two parts, RegUsageInfoCollector is the MachineFunction Pass that runs post-RA and collect the list of clobbered registers to produce a register mask. An immutable pass, RegisterUsageInfo, stores the RegMask produced by RegUsageInfoCollector, and keep them available. A future tranformation pass will use this information to update every call-sites after instruction selection. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D20769 llvm-svn: 272403
93 lines
2.9 KiB
C++
93 lines
2.9 KiB
C++
//===- RegisterUsageInfo.cpp - Register Usage Informartion Storage --------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
///
|
|
/// This pass is required to take advantage of the interprocedural register
|
|
/// allocation infrastructure.
|
|
///
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/CodeGen/RegisterUsageInfo.h"
|
|
#include "llvm/CodeGen/MachineOperand.h"
|
|
#include "llvm/IR/Module.h"
|
|
#include "llvm/Support/Debug.h"
|
|
#include "llvm/Support/raw_ostream.h"
|
|
|
|
using namespace llvm;
|
|
|
|
#define DEBUG_TYPE "ip-regalloc"
|
|
|
|
cl::opt<bool> DumpRegUsage(
|
|
"print-regusage", cl::init(false), cl::Hidden,
|
|
cl::desc("print register usage details collected for analysis."));
|
|
|
|
INITIALIZE_PASS(PhysicalRegisterUsageInfo, "reg-usage-info",
|
|
"Register Usage Informartion Stroage", false, true)
|
|
|
|
char PhysicalRegisterUsageInfo::ID = 0;
|
|
|
|
void PhysicalRegisterUsageInfo::anchor() {}
|
|
|
|
bool PhysicalRegisterUsageInfo::doInitialization(Module &M) {
|
|
RegMasks.grow(M.size());
|
|
return false;
|
|
}
|
|
|
|
bool PhysicalRegisterUsageInfo::doFinalization(Module &M) {
|
|
if (DumpRegUsage)
|
|
print(errs());
|
|
|
|
RegMasks.shrink_and_clear();
|
|
return false;
|
|
}
|
|
|
|
void PhysicalRegisterUsageInfo::storeUpdateRegUsageInfo(
|
|
const Function *FP, std::vector<uint32_t> RegMask) {
|
|
assert(FP != nullptr && "Function * can't be nullptr.");
|
|
RegMasks[FP] = std::move(RegMask);
|
|
}
|
|
|
|
const std::vector<uint32_t> *
|
|
PhysicalRegisterUsageInfo::getRegUsageInfo(const Function *FP) {
|
|
if (RegMasks.find(FP) != RegMasks.end())
|
|
return &(RegMasks.find(FP)->second);
|
|
return nullptr;
|
|
}
|
|
|
|
void PhysicalRegisterUsageInfo::print(raw_ostream &OS, const Module *M) const {
|
|
const TargetRegisterInfo *TRI;
|
|
|
|
typedef std::pair<const Function *, std::vector<uint32_t>> FuncPtrRegMaskPair;
|
|
|
|
SmallVector<const FuncPtrRegMaskPair *, 64> FPRMPairVector;
|
|
|
|
// Create a vector of pointer to RegMasks entries
|
|
for (const auto &RegMask : RegMasks)
|
|
FPRMPairVector.push_back(&RegMask);
|
|
|
|
// sort the vector to print analysis in alphabatic order of function name.
|
|
std::sort(
|
|
FPRMPairVector.begin(), FPRMPairVector.end(),
|
|
[](const FuncPtrRegMaskPair *A, const FuncPtrRegMaskPair *B) -> bool {
|
|
return A->first->getName() < B->first->getName();
|
|
});
|
|
|
|
for (const FuncPtrRegMaskPair *FPRMPair : FPRMPairVector) {
|
|
OS << FPRMPair->first->getName() << " "
|
|
<< "Clobbered Registers: ";
|
|
TRI = TM->getSubtarget<TargetSubtargetInfo>(*(FPRMPair->first))
|
|
.getRegisterInfo();
|
|
|
|
for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
|
|
if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg))
|
|
OS << TRI->getName(PReg) << " ";
|
|
}
|
|
OS << "\n";
|
|
}
|
|
}
|