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86fa0255b2
llvm-mirror/test
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Tim Northover 86fa0255b2 AArch64: TableGenerate system instruction operands. 
The way the named arguments for various system instructions are handled at the
moment has a few problems:

  - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
  - That weird Mapping class that I have no idea what I was on when I thought
    it was a good idea.
  - Searches are performed linearly through the entire list.
  - We print absolutely all registers in upper-case, even though some are
    canonically mixed case (SPSel for example).
  - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
    to comments in our implementation, with a slightly opaque hex value
    indicating the canonical encoding LLVM will use.

This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.

llvm-svn: 274576
2016-07-05 21:23:04 +00:00
..
Analysis [PowerPC] - Legalize vector types by widening instead of integer promotion 2016-07-05 09:22:29 +00:00
Assembler [codeview] Add DISubprogram::ThisAdjustment 2016-07-01 02:41:21 +00:00
Bindings Add writeonly IR attribute 2016-07-04 08:01:29 +00:00
Bitcode Add writeonly IR attribute 2016-07-04 08:01:29 +00:00
BugPoint
CodeGen AArch64: TableGenerate system instruction operands. 2016-07-05 21:23:04 +00:00
DebugInfo [codeview] Set the Nested and Scoped ClassOptions based on the scope chain 2016-07-02 00:11:07 +00:00
Examples
ExecutionEngine ExecutionEngine: add preliminary support for COFF ARM 2016-06-24 14:11:44 +00:00
Feature IR: Introduce local_unnamed_addr attribute. 2016-06-14 21:01:22 +00:00
FileCheck Make check lines not match themselves. 2016-06-16 19:38:48 +00:00
Instrumentation [esan|cfrag] Add counters for struct array accesses 2016-07-02 03:25:37 +00:00
Integer
JitListener
LibDriver
Linker Don't verify inputs to the Linker if ODR merging. 2016-06-29 18:31:48 +00:00
LTO Add writeonly IR attribute 2016-07-04 08:01:29 +00:00
MC AArch64: TableGenerate system instruction operands. 2016-07-05 21:23:04 +00:00
Object Finish cleaning up most of the error handling in libObject’s MachOUniversalBinary 2016-06-28 23:16:13 +00:00
ObjectYAML [YAML] Fix YAML tags appearing before the start of sequence elements 2016-06-28 21:10:26 +00:00
Other [PM] Improve the debugging and logging facilities of the CGSCC bits of 2016-06-27 23:26:08 +00:00
SymbolRewriter
TableGen [Target] Introduce a generic opcode for bitwise OR: G_OR. 2016-06-08 16:12:19 +00:00
ThinLTO/X86 [ThinLTO] Resolve LinkOnceAny 2016-05-26 14:16:52 +00:00
tools test: relax the match on the timestamp 2016-07-05 01:14:53 +00:00
Transforms [InstCombine] enable vector select of bools -> logic folds 2016-07-03 14:34:39 +00:00
Unit
Verifier Add writeonly IR attribute 2016-07-04 08:01:29 +00:00
YAMLParser
.clang-format
CMakeLists.txt [cmake] Fix builds with LLVM_ENABLE_PIC=0 2016-06-02 16:29:07 +00:00
lit.cfg
lit.site.cfg.in
TestRunner.sh