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a8aaad127d
When we are scheduling the load and addi, if all other heuristic didn't take effect, we will try to schedule the addi before the load, to hide the latency, and avoid the true dependency added by RA. And this only take effects for Power9. Differential Revision: https://reviews.llvm.org/D61930 llvm-svn: 361600
50 lines
1.7 KiB
C++
50 lines
1.7 KiB
C++
//===- PPCMachineScheduler.h - Custom PowerPC MI scheduler --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Custom PowerPC MI scheduler.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H
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#define LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H
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#include "llvm/CodeGen/MachineScheduler.h"
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namespace llvm {
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/// A MachineSchedStrategy implementation for PowerPC pre RA scheduling.
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class PPCPreRASchedStrategy : public GenericScheduler {
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public:
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PPCPreRASchedStrategy(const MachineSchedContext *C) :
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GenericScheduler(C) {}
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protected:
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void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand,
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SchedBoundary *Zone) const override;
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private:
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bool biasAddiLoadCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary &Zone) const;
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};
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/// A MachineSchedStrategy implementation for PowerPC post RA scheduling.
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class PPCPostRASchedStrategy : public PostGenericScheduler {
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public:
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PPCPostRASchedStrategy(const MachineSchedContext *C) :
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PostGenericScheduler(C) {}
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protected:
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void initialize(ScheduleDAGMI *Dag) override;
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SUnit *pickNode(bool &IsTopNode) override;
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void enterMBB(MachineBasicBlock *MBB) override;
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void leaveMBB() override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H
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