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8957a377cc
Based on the discussion in http://lists.llvm.org/pipermail/llvm-dev/2019-October/135574.html, the conclusion was reached that the ARM backend should produce vcmp instead of vcmpe instructions by default, i.e. not be producing an Invalid Operation exception when either arguments in a floating point compare are quiet NaNs. In the future, after constrained floating point intrinsics for floating point compare have been introduced, vcmpe instructions probably should be produced for those intrinsics - depending on the exact semantics they'll be defined to have. This patch logically consists of the following parts: - Revert http://llvm.org/viewvc/llvm-project?rev=294945&view=rev and http://llvm.org/viewvc/llvm-project?rev=294968&view=rev, which implemented fine-tuning for when to produce vcmpe (i.e. not do it for equality comparisons). The complexity introduced by those patches isn't needed anymore if we just always produce vcmp instead. Maybe these patches need to be reintroduced again once support is needed to map potential LLVM-IR constrained floating point compare intrinsics to the ARM instruction set. - Simply select vcmp, instead of vcmpe, see simple changes in lib/Target/ARM/ARMInstrVFP.td - Adapt lots of tests that tested for vcmpe (instead of vcmp). For all of these test, the intent of what is tested for isn't related to whether the vcmp should produce an Invalid Operation exception or not. Fixes PR43374. Differential Revision: https://reviews.llvm.org/D68463 llvm-svn: 374025
101 lines
3.4 KiB
LLVM
101 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR
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; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8,+neon,+neonfp | FileCheck %s --check-prefixes=CHECK,NEON
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define arm_aapcs_vfpcc float @foo0(float %a0) local_unnamed_addr {
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; CHECK-LABEL: foo0:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcmp.f32 s0, #0
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; CHECK-NEXT: vmov.f32 s2, #5.000000e-01
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vmov.f32 s4, #-5.000000e-01
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; CHECK-NEXT: it mi
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; CHECK-NEXT: vmovmi.f32 s2, s4
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; CHECK-NEXT: vmov.f32 s0, s2
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; CHECK-NEXT: bx lr
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%1 = fcmp nsz olt float %a0, 0.000000e+00
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%2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
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ret float %2
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}
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define arm_aapcs_vfpcc float @float1(float %a0) local_unnamed_addr {
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; CHECK-LABEL: float1:
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; CHECK: @ %bb.0: @ %.end
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; CHECK-NEXT: vmov.f32 s2, #1.000000e+00
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; CHECK-NEXT: vmov.f32 s4, #5.000000e-01
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; CHECK-NEXT: vmov.f32 s6, #-5.000000e-01
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; CHECK-NEXT: vcmp.f32 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f32 s0, s6, s4
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; CHECK-NEXT: bx lr
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br i1 undef, label %.end, label %1
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%2 = fcmp nsz olt float %a0, 1.000000e+00
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%3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
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br label %.end
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.end:
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%4 = phi float [ undef, %0 ], [ %3, %1]
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ret float %4
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}
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define arm_aapcs_vfpcc float @float128(float %a0) local_unnamed_addr {
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; VMOVSR-LABEL: float128:
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; VMOVSR: @ %bb.0:
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; VMOVSR-NEXT: mov.w r0, #1124073472
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; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01
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; VMOVSR-NEXT: vmov s2, r0
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; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01
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; VMOVSR-NEXT: vcmp.f32 s2, s0
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; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr
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; VMOVSR-NEXT: vselgt.f32 s0, s6, s4
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; VMOVSR-NEXT: bx lr
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;
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; NEON-LABEL: float128:
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; NEON: @ %bb.0:
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; NEON-NEXT: mov.w r0, #1124073472
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; NEON-NEXT: vmov.f32 s2, #5.000000e-01
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; NEON-NEXT: vmov d3, r0, r0
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; NEON-NEXT: vmov.f32 s4, #-5.000000e-01
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; NEON-NEXT: vcmp.f32 s6, s0
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; NEON-NEXT: vmrs APSR_nzcv, fpscr
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; NEON-NEXT: vselgt.f32 s0, s4, s2
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; NEON-NEXT: bx lr
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%1 = fcmp nsz olt float %a0, 128.000000e+00
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%2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
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ret float %2
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}
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define arm_aapcs_vfpcc double @double1(double %a0) local_unnamed_addr {
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; CHECK-LABEL: double1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.f64 d18, #1.000000e+00
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; CHECK-NEXT: vcmp.f64 d18, d0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vmov.f64 d16, #5.000000e-01
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; CHECK-NEXT: vmov.f64 d17, #-5.000000e-01
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; CHECK-NEXT: vselgt.f64 d0, d17, d16
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; CHECK-NEXT: bx lr
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%1 = fcmp nsz olt double %a0, 1.000000e+00
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%2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
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ret double %2
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}
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define arm_aapcs_vfpcc double @double128(double %a0) local_unnamed_addr {
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; CHECK-LABEL: double128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: movs r1, #0
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; CHECK-NEXT: movt r0, #16480
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; CHECK-NEXT: vmov.f64 d16, #5.000000e-01
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; CHECK-NEXT: vmov d18, r1, r0
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; CHECK-NEXT: vcmp.f64 d18, d0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vmov.f64 d17, #-5.000000e-01
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; CHECK-NEXT: vselgt.f64 d0, d17, d16
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; CHECK-NEXT: bx lr
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%1 = fcmp nsz olt double %a0, 128.000000e+00
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%2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
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ret double %2
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}
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