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https://github.com/RPCS3/llvm-mirror.git
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dd53274771
This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
79 lines
2.4 KiB
LLVM
79 lines
2.4 KiB
LLVM
; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE
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; RUN: not --crash llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE
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; MCORE: LLVM ERROR: Invalid register name "cpsr".
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define i32 @read_cpsr() nounwind {
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; ACORE-LABEL: read_cpsr:
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; ACORE: mrs r0, apsr
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%reg = call i32 @llvm.read_register.i32(metadata !1)
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ret i32 %reg
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}
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define i32 @read_aclass_registers() nounwind {
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entry:
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; ACORE-LABEL: read_aclass_registers:
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; ACORE: mrs r0, apsr
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; ACORE: mrs r1, spsr
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%0 = call i32 @llvm.read_register.i32(metadata !0)
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%1 = call i32 @llvm.read_register.i32(metadata !1)
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%add1 = add i32 %1, %0
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%2 = call i32 @llvm.read_register.i32(metadata !2)
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%add2 = add i32 %add1, %2
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ret i32 %add2
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}
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define void @write_aclass_registers(i32 %x) nounwind {
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entry:
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; ACORE-LABEL: write_aclass_registers:
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; ACORE: msr APSR_nzcvq, r0
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; ACORE: msr APSR_g, r0
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; ACORE: msr APSR_nzcvqg, r0
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; ACORE: msr CPSR_c, r0
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; ACORE: msr CPSR_x, r0
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; ACORE: msr APSR_g, r0
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; ACORE: msr APSR_nzcvq, r0
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; ACORE: msr CPSR_fsxc, r0
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; ACORE: msr SPSR_c, r0
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; ACORE: msr SPSR_x, r0
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; ACORE: msr SPSR_s, r0
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; ACORE: msr SPSR_f, r0
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; ACORE: msr SPSR_fsxc, r0
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call void @llvm.write_register.i32(metadata !3, i32 %x)
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call void @llvm.write_register.i32(metadata !4, i32 %x)
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call void @llvm.write_register.i32(metadata !5, i32 %x)
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call void @llvm.write_register.i32(metadata !6, i32 %x)
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call void @llvm.write_register.i32(metadata !7, i32 %x)
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call void @llvm.write_register.i32(metadata !8, i32 %x)
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call void @llvm.write_register.i32(metadata !9, i32 %x)
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call void @llvm.write_register.i32(metadata !10, i32 %x)
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call void @llvm.write_register.i32(metadata !11, i32 %x)
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call void @llvm.write_register.i32(metadata !12, i32 %x)
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call void @llvm.write_register.i32(metadata !13, i32 %x)
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call void @llvm.write_register.i32(metadata !14, i32 %x)
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call void @llvm.write_register.i32(metadata !15, i32 %x)
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ret void
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}
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declare i32 @llvm.read_register.i32(metadata) nounwind
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declare void @llvm.write_register.i32(metadata, i32) nounwind
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!0 = !{!"apsr"}
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!1 = !{!"cpsr"}
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!2 = !{!"spsr"}
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!3 = !{!"apsr_nzcvq"}
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!4 = !{!"apsr_g"}
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!5 = !{!"apsr_nzcvqg"}
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!6 = !{!"cpsr_c"}
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!7 = !{!"cpsr_x"}
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!8 = !{!"cpsr_s"}
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!9 = !{!"cpsr_f"}
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!10 = !{!"cpsr_cxsf"}
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!11 = !{!"spsr_c"}
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!12 = !{!"spsr_x"}
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!13 = !{!"spsr_s"}
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!14 = !{!"spsr_f"}
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!15 = !{!"spsr_cxsf"}
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