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Many Thumb1 instructions are defined to set CPSR if executed outside an IT block, but leave it alone from inside one. In MachineIR this is represented by whether an optional register is CPSR or NoReg (0), and affects how the instructions are printed. This sets the instruction to the appropriate form during if-conversion.
25 lines
575 B
LLVM
25 lines
575 B
LLVM
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 < %s | FileCheck %s
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; RUN: llc -mtriple=thumbv8 < %s | FileCheck %s
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; PR11107
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define i32 @test(i32 %a, i32 %b) {
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entry:
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%cmp1 = icmp slt i32 %a, 0
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%sub1 = sub nsw i32 0, %a
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%abs1 = select i1 %cmp1, i32 %sub1, i32 %a
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%cmp2 = icmp slt i32 %b, 0
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%sub2 = sub nsw i32 0, %b
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%abs2 = select i1 %cmp2, i32 %sub2, i32 %b
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%add = add nsw i32 %abs1, %abs2
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ret i32 %add
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}
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; CHECK: cmp
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; CHECK-NEXT: it mi
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; CHECK-NEXT: rsbmi
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; CHECK-NEXT: cmp
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; CHECK-NEXT: it mi
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; CHECK-NEXT: rsb{{s?}}mi
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