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1941ea029d
Fill in the gaps for vrev32.16 f16 patterns, extending the existing i16 patterns. Differential Revision: https://reviews.llvm.org/D69508
350 lines
13 KiB
LLVM
350 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi -mattr=+neon,+fullfp16 %s -o - | FileCheck %s
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define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: test_vrev64D8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev64.8 d16, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
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; CHECK-LABEL: test_vrev64D16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev64.16 d16, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i16> %tmp2
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}
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define <4 x half> @test_vrev64Df16(<4 x half>* %A) nounwind {
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; CHECK-LABEL: test_vrev64Df16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev64.16 d16, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x half>, <4 x half>* %A
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%tmp2 = shufflevector <4 x half> %tmp1, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x half> %tmp2
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}
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define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
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; CHECK-LABEL: test_vrev64D32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev64.32 d16, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x i32> %tmp2
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}
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define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
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; CHECK-LABEL: test_vrev64Df:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev64.32 d16, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x float> %tmp2
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}
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define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
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; CHECK-LABEL: test_vrev64Q8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev64.8 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
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; CHECK-LABEL: test_vrev64Q16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev64.16 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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ret <8 x i16> %tmp2
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}
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define <8 x half> @test_vrev64Qf16(<8 x half>* %A) nounwind {
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; CHECK-LABEL: test_vrev64Qf16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev64.16 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x half>, <8 x half>* %A
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%tmp2 = shufflevector <8 x half> %tmp1, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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ret <8 x half> %tmp2
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}
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define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
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; CHECK-LABEL: test_vrev64Q32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev64.32 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i32> %tmp2
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}
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define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
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; CHECK-LABEL: test_vrev64Qf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev64.32 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x float> %tmp2
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}
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define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: test_vrev32D8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev32.8 d16, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
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; CHECK-LABEL: test_vrev32D16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev32.16 d16, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i16> %tmp2
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}
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define <4 x half> @test_vrev32Df16(<4 x half>* %A) nounwind {
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; CHECK-LABEL: test_vrev32Df16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev32.16 d16, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x half>, <4 x half>* %A
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%tmp2 = shufflevector <4 x half> %tmp1, <4 x half> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x half> %tmp2
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}
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define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
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; CHECK-LABEL: test_vrev32Q8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev32.8 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
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; CHECK-LABEL: test_vrev32Q16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev32.16 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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ret <8 x i16> %tmp2
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}
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define <8 x half> @test_vrev32Qf16(<8 x half>* %A) nounwind {
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; CHECK-LABEL: test_vrev32Qf16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev32.16 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x half>, <8 x half>* %A
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%tmp2 = shufflevector <8 x half> %tmp1, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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ret <8 x half> %tmp2
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}
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define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: test_vrev16D8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev16.8 d16, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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ret <8 x i8> %tmp2
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}
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define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
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; CHECK-LABEL: test_vrev16Q8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev16.8 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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ret <16 x i8> %tmp2
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}
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; Undef shuffle indices should not prevent matching to VREV:
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define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: test_vrev64D8_undef:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev64.8 d16, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
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ret <8 x i8> %tmp2
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}
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define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
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; CHECK-LABEL: test_vrev32Q16_undef:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev32.16 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
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ret <8 x i16> %tmp2
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}
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define <8 x half> @test_vrev32Qf16_undef(<8 x half>* %A) nounwind {
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; CHECK-LABEL: test_vrev32Qf16_undef:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vrev32.16 q8, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x half>, <8 x half>* %A
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%tmp2 = shufflevector <8 x half> %tmp1, <8 x half> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
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ret <8 x half> %tmp2
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}
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; A vcombine feeding a VREV should not obscure things. Radar 8597007.
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define void @test_with_vcombine(<4 x float>* %v) nounwind {
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; CHECK-LABEL: test_with_vcombine:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: vadd.f32 d18, d17, d17
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; CHECK-NEXT: vrev64.32 d16, d16
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; CHECK-NEXT: vrev64.32 d17, d18
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x float>, <4 x float>* %v, align 16
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%tmp2 = bitcast <4 x float> %tmp1 to <2 x double>
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%tmp3 = extractelement <2 x double> %tmp2, i32 0
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%tmp4 = bitcast double %tmp3 to <2 x float>
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%tmp5 = extractelement <2 x double> %tmp2, i32 1
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%tmp6 = bitcast double %tmp5 to <2 x float>
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%tmp7 = fadd <2 x float> %tmp6, %tmp6
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%tmp8 = shufflevector <2 x float> %tmp4, <2 x float> %tmp7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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store <4 x float> %tmp8, <4 x float>* %v, align 16
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ret void
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}
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; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
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; to <2 x i16> when stored to memory.
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define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
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; CHECK-LABEL: test_vrev64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vld1.32 {d16, d17}, [r0]
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; CHECK-NEXT: vmov.u16 r0, d17[2]
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; CHECK-NEXT: vmov.u16 r2, d17[1]
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; CHECK-NEXT: vmov.32 d16[0], r0
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; CHECK-NEXT: vmov.32 d16[1], r2
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; CHECK-NEXT: vuzp.16 d16, d17
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; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32]
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; CHECK-NEXT: mov pc, lr
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entry:
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%0 = bitcast <4 x i16>* %source to <8 x i16>*
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%tmp2 = load <8 x i16>, <8 x i16>* %0, align 4
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%tmp3 = extractelement <8 x i16> %tmp2, i32 6
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%tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
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%tmp9 = extractelement <8 x i16> %tmp2, i32 5
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%tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1
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store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
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ret void
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}
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; Test vrev of float4
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define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp {
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; CHECK-LABEL: float_vrev64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q8, #0x0
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; CHECK-NEXT: vld1.32 {d18, d19}, [r0]
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; CHECK-NEXT: add r0, r1, #176
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; CHECK-NEXT: vext.32 q8, q9, q8, #3
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; CHECK-NEXT: vrev64.32 q8, q8
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; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
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; CHECK-NEXT: mov pc, lr
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entry:
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%0 = bitcast float* %source to <4 x float>*
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%tmp2 = load <4 x float>, <4 x float>* %0, align 4
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%tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
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%arrayidx8 = getelementptr inbounds <4 x float>, <4 x float>* %dest, i32 11
|
|
store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
|
|
ret void
|
|
}
|
|
|
|
define <4 x i32> @test_vrev32_bswap(<4 x i32> %source) nounwind {
|
|
; CHECK-LABEL: test_vrev32_bswap:
|
|
; CHECK: @ %bb.0:
|
|
; CHECK-NEXT: vmov d17, r2, r3
|
|
; CHECK-NEXT: vmov d16, r0, r1
|
|
; CHECK-NEXT: vrev32.8 q8, q8
|
|
; CHECK-NEXT: vmov r0, r1, d16
|
|
; CHECK-NEXT: vmov r2, r3, d17
|
|
; CHECK-NEXT: mov pc, lr
|
|
%bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %source)
|
|
ret <4 x i32> %bswap
|
|
}
|
|
|
|
declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
|