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5da66b880e
The addition of `inverse_throughput` mode highlighted the disjointedness of snippet generators and benchmark runners because it used the `UopsSnippetGenerator` with the `LatencyBenchmarkRunner`. To keep the code consistent tie the snippet generators to parallelization/serialization rather than their benchmark runners. Renaming `LatencySnippetGenerator` -> `SerialSnippetGenerator`. Renaming `UopsSnippetGenerator` -> `ParallelSnippetGenerator`. Differential Revision: https://reviews.llvm.org/D72928
128 lines
4.3 KiB
C++
128 lines
4.3 KiB
C++
//===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "../Common/AssemblerUtils.h"
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#include "LlvmState.h"
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#include "MCInstrDescView.h"
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#include "MipsInstrInfo.h"
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#include "ParallelSnippetGenerator.h"
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#include "RegisterAliasing.h"
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#include "SerialSnippetGenerator.h"
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#include "TestBase.h"
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#include <unordered_set>
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namespace llvm {
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namespace exegesis {
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namespace {
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using testing::AnyOf;
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using testing::ElementsAre;
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using testing::HasSubstr;
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using testing::SizeIs;
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MATCHER(IsInvalid, "") { return !arg.isValid(); }
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MATCHER(IsReg, "") { return arg.isReg(); }
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class MipsSnippetGeneratorTest : public MipsTestBase {};
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template <typename SnippetGeneratorT>
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class SnippetGeneratorTest : public MipsSnippetGeneratorTest {
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protected:
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SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
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std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
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randomGenerator().seed(0); // Initialize seed.
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const Instruction &Instr = State.getIC().getInstr(Opcode);
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auto CodeTemplateOrError = Generator.generateCodeTemplates(
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Instr, State.getRATC().emptyRegisters());
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EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
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return std::move(CodeTemplateOrError.get());
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}
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SnippetGeneratorT Generator;
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};
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using SerialSnippetGeneratorTest = SnippetGeneratorTest<SerialSnippetGenerator>;
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using ParallelSnippetGeneratorTest =
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SnippetGeneratorTest<ParallelSnippetGenerator>;
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TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
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// - ADD
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// - Op0 Explicit Def RegClass(GPR32)
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// - Op1 Explicit Use RegClass(GPR32)
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// - Op2 Explicit Use RegClass(GPR32)
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// - Var0 [Op0]
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// - Var1 [Op1]
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// - Var2 [Op2]
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// - hasAliasingRegisters
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const unsigned Opcode = Mips::ADD;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
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ASSERT_THAT(CT.Instructions, SizeIs(1));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
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EXPECT_THAT(IT.getVariableValues(),
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AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
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ElementsAre(IsReg(), IsReg(), IsInvalid())))
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<< "Op0 is either set to Op1 or to Op2";
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}
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TEST_F(SerialSnippetGeneratorTest,
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ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
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// - XOR
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// - Op0 Explicit Def RegClass(GPR32)
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// - Op1 Explicit Use RegClass(GPR32)
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// - Op2 Explicit Use RegClass(GPR32)
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// - Var0 [Op0]
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// - Var1 [Op1]
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// - Var2 [Op2]
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// - hasAliasingRegisters
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randomGenerator().seed(0); // Initialize seed.
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const Instruction &Instr = State.getIC().getInstr(Mips::XOR);
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auto AllRegisters = State.getRATC().emptyRegisters();
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AllRegisters.flip();
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auto Error = Generator.generateCodeTemplates(Instr, AllRegisters).takeError();
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EXPECT_TRUE((bool)Error);
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consumeError(std::move(Error));
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}
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TEST_F(ParallelSnippetGeneratorTest, MemoryUse) {
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// LB reads from memory.
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// - LB
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// - Op0 Explicit Def RegClass(GPR32)
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// - Op1 Explicit Use Memory RegClass(MSA128F16)
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// - Op2 Explicit Use Memory
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// - Var0 [Op0]
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// - Var1 [Op1]
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// - Var2 [Op2]
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// - hasMemoryOperands
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const unsigned Opcode = Mips::LB;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Info,
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HasSubstr("instruction is parallel, repeating a random one."));
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EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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ASSERT_THAT(CT.Instructions,
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SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
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EXPECT_EQ(IT.getVariableValues()[0].getReg(), 0u);
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EXPECT_EQ(IT.getVariableValues()[2].getImm(), 0);
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}
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} // namespace
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} // namespace exegesis
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} // namespace llvm
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