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8dd0e2fb27
the TableGen descriptions; all unset bits are thus errors. * As a result, found and fixed instructions where some operands were not actually assigned into the right portion of the instruction. llvm-svn: 7074
137 lines
3.1 KiB
C++
137 lines
3.1 KiB
C++
//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
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// vim:ft=cpp
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//===----------------------------------------------------------------------===//
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//----------------------- F4 classes -----------------------------------------
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// F4 - Common superclass of all F4 instructions. All instructions have an op3
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// field.
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class F4 : InstV9 {
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bits<6> op3;
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set Inst{24-19} = op3;
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}
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// F4_rs1 - Common class of instructions that use an rs1 field
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class F4_rs1 : F4 {
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bits<5> rs1;
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set Inst{18-14} = rs1;
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}
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// F4_rs1rs2 - Common class of instructions that have rs1 and rs2 fields
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class F4_rs1rs2 : F4_rs1 {
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bits<5> rs2;
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set Inst{4-0} = rs2;
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}
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// F4_rs1rs2rd - Common class of instructions that have 3 register operands
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class F4_rs1rs2rd : F4_rs1rs2 {
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bits<5> rd;
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set Inst{29-25} = rd;
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}
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// F4_rs1rs2rd - Common class of instructions that have 2 reg and 1 imm operand
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class F4_rs1simm11rd : F4_rs1 {
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bits<11> simm11;
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bits<5> rd;
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set Inst{10-0} = simm11;
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set Inst{29-25} = rd;
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}
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// F4_cc - Common class of instructions that have a cond field
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class F4_cond : F4 {
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bits<4> cond;
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set Inst{17-14} = cond;
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}
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// F4_cc - Common class of instructions that have cc register as first operand
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class F4_condcc : F4_cond {
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bits<3> cc;
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set Inst{18} = cc{2};
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set Inst{12} = cc{1};
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set Inst{11} = cc{0};
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}
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// Actual F4 instruction classes
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//
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class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1rs2rd {
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bits<2> cc;
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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set Inst{13} = 0; // i bit
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set Inst{12-11} = cc;
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set Inst{10-5} = 0; // don't care
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}
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class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1simm11rd {
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bits<2> cc;
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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set Inst{13} = 1; // i bit
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set Inst{12-11} = cc;
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}
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class F4_3<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
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string name> : F4_condcc {
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bits<5> rs2;
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bits<5> rd;
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set op = opVal;
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set op3 = op3Val;
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set cond = condVal;
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set Name = name;
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set Inst{29-25} = rd;
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set Inst{13} = 0; // i bit
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set Inst{10-5} = 0; // don't care
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set Inst{4-0} = rs2;
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}
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class F4_4<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
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string name> : F4_condcc {
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bits<11> sim11;
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bits<5> rd;
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set op = opVal;
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set op3 = op3Val;
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set cond = condVal;
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set Name = name;
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set Inst{29-25} = rd;
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set Inst{13} = 1; // i bit
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set Inst{10-0} = sim11;
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}
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// FIXME: class F4_5
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class F4_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
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bits<5> opf_lowVal, string name> : F4_rs1rs2rd {
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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set Inst{13} = 0;
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set Inst{12-10} = rcondVal;
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set Inst{9-5} = opf_lowVal;
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}
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class F4_7<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
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bits<6> opf_lowVal, string name> : F4_cond {
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bits<3> cc;
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bits<5> rs2;
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bits<5> rd;
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set op = opVal;
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set op3 = op3Val;
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set cond = condVal;
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set Name = name;
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set Inst{29-25} = rd;
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set Inst{18} = 0;
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set Inst{13-11} = cc;
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set Inst{10-5} = opf_lowVal;
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set Inst{4-0} = rs2;
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}
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// FIXME: F4 classes 8-9
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