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882f4d03f6
No test cases. These patterns will get tested along with dsp intrinsics. llvm-svn: 164746
44 lines
1.8 KiB
TableGen
44 lines
1.8 KiB
TableGen
//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips DSP ASE instructions.
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//
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//===----------------------------------------------------------------------===//
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// ImmLeaf
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def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
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def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
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def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
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def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
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def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
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def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
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// Patterns.
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class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
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Pat<pattern, result>, Requires<[pred]>;
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class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
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RegisterClass SrcRC> :
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DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
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(COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
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def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
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def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
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def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
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def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
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def : DSPPat<(v2i16 (load addr:$a)),
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(v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
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def : DSPPat<(v4i8 (load addr:$a)),
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(v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
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def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
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(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
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def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
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(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
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