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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 22:42:46 +02:00
llvm-mirror/test/MC/Disassembler
Colin LeMahieu 88461f5b7a [Hexagon] Adding encoding bits for add opcode.
Adding llvm-mc tests.
Removing unit tests.

http://reviews.llvm.org/D5624

llvm-svn: 220427
2014-10-22 20:58:35 +00:00
..
AArch64 Condition codes AL and NV are invalid in the aliases that use 2014-06-10 13:11:35 +00:00
ARM Thumb2 M-class MSR instruction support changes 2014-09-01 11:25:07 +00:00
Hexagon [Hexagon] Adding encoding bits for add opcode. 2014-10-22 20:58:35 +00:00
Mips [mips] Fix disassembly of [ls][wd]c[23], cache, and pref 2014-10-01 08:26:55 +00:00
PowerPC [PowerPC] Add support for dcbtst and icbt (prefetch) 2014-08-23 23:21:04 +00:00
Sparc Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
SystemZ [SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA 2014-07-10 11:00:55 +00:00
X86 [X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit mode for certain instructions it shouldn't. 2014-10-07 07:29:50 +00:00
XCore Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00