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https://github.com/RPCS3/llvm-mirror.git
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5f91239343
This patch uses the mechanism from D62995 to strengthen the definitions of the reduction intrinsics by letting the scalar result/accumulator type be overloaded from the vector element type. For example: ; The LLVM LangRef specifies that the scalar result must equal the ; vector element type, but this is not checked/enforced by LLVM. declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a) This patch changes that into: declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a) Which has the type-constraint more explicit and causes LLVM to check the result type with the vector element type. Reviewers: RKSimon, arsenm, rnk, greened, aemerson Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62996 llvm-svn: 363240
229 lines
8.2 KiB
LLVM
229 lines
8.2 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-linux--gnu -aarch64-neon-syntax=generic | FileCheck %s
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>)
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declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>)
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declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>)
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declare i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8>)
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declare i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16>)
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declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>)
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declare i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8>)
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declare i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16>)
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declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>)
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declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
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declare i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16>)
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declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>)
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declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float>)
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declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
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; CHECK-LABEL: smax_B
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; CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
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define i8 @smax_B(<16 x i8>* nocapture readonly %arr) {
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%arr.load = load <16 x i8>, <16 x i8>* %arr
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%r = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> %arr.load)
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ret i8 %r
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}
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; CHECK-LABEL: smax_H
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; CHECK: smaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
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define i16 @smax_H(<8 x i16>* nocapture readonly %arr) {
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%arr.load = load <8 x i16>, <8 x i16>* %arr
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%r = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> %arr.load)
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ret i16 %r
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}
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; CHECK-LABEL: smax_S
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; CHECK: smaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
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define i32 @smax_S(<4 x i32> * nocapture readonly %arr) {
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%arr.load = load <4 x i32>, <4 x i32>* %arr
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%r = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %arr.load)
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ret i32 %r
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}
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; CHECK-LABEL: umax_B
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; CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
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define i8 @umax_B(<16 x i8>* nocapture readonly %arr) {
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%arr.load = load <16 x i8>, <16 x i8>* %arr
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%r = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> %arr.load)
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ret i8 %r
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}
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; CHECK-LABEL: umax_H
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; CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
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define i16 @umax_H(<8 x i16>* nocapture readonly %arr) {
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%arr.load = load <8 x i16>, <8 x i16>* %arr
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%r = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> %arr.load)
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ret i16 %r
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}
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; CHECK-LABEL: umax_S
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; CHECK: umaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
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define i32 @umax_S(<4 x i32>* nocapture readonly %arr) {
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%arr.load = load <4 x i32>, <4 x i32>* %arr
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%r = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %arr.load)
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ret i32 %r
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}
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; CHECK-LABEL: smin_B
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; CHECK: sminv {{b[0-9]+}}, {{v[0-9]+}}.16b
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define i8 @smin_B(<16 x i8>* nocapture readonly %arr) {
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%arr.load = load <16 x i8>, <16 x i8>* %arr
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%r = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> %arr.load)
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ret i8 %r
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}
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; CHECK-LABEL: smin_H
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; CHECK: sminv {{h[0-9]+}}, {{v[0-9]+}}.8h
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define i16 @smin_H(<8 x i16>* nocapture readonly %arr) {
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%arr.load = load <8 x i16>, <8 x i16>* %arr
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%r = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> %arr.load)
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ret i16 %r
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}
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; CHECK-LABEL: smin_S
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; CHECK: sminv {{s[0-9]+}}, {{v[0-9]+}}.4s
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define i32 @smin_S(<4 x i32>* nocapture readonly %arr) {
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%arr.load = load <4 x i32>, <4 x i32>* %arr
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%r = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %arr.load)
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ret i32 %r
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}
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; CHECK-LABEL: umin_B
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; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
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define i8 @umin_B(<16 x i8>* nocapture readonly %arr) {
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%arr.load = load <16 x i8>, <16 x i8>* %arr
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%r = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> %arr.load)
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ret i8 %r
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}
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; CHECK-LABEL: umin_H
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; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
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define i16 @umin_H(<8 x i16>* nocapture readonly %arr) {
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%arr.load = load <8 x i16>, <8 x i16>* %arr
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%r = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> %arr.load)
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ret i16 %r
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}
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; CHECK-LABEL: umin_S
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; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
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define i32 @umin_S(<4 x i32>* nocapture readonly %arr) {
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%arr.load = load <4 x i32>, <4 x i32>* %arr
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%r = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %arr.load)
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ret i32 %r
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}
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; CHECK-LABEL: fmaxnm_S
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; CHECK: fmaxnmv
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define float @fmaxnm_S(<4 x float>* nocapture readonly %arr) {
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%arr.load = load <4 x float>, <4 x float>* %arr
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%r = call nnan float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %arr.load)
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ret float %r
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}
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; CHECK-LABEL: fminnm_S
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; CHECK: fminnmv
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define float @fminnm_S(<4 x float>* nocapture readonly %arr) {
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%arr.load = load <4 x float>, <4 x float>* %arr
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%r = call nnan float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %arr.load)
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ret float %r
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}
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declare i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16>)
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define i16 @oversized_umax_256(<16 x i16>* nocapture readonly %arr) {
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; CHECK-LABEL: oversized_umax_256
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; CHECK: umax [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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; CHECK: umaxv {{h[0-9]+}}, [[V0]]
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%arr.load = load <16 x i16>, <16 x i16>* %arr
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%r = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> %arr.load)
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ret i16 %r
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}
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declare i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32>)
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define i32 @oversized_umax_512(<16 x i32>* nocapture readonly %arr) {
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; CHECK-LABEL: oversized_umax_512
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; CHECK: umax v
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; CHECK-NEXT: umax v
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; CHECK-NEXT: umax [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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; CHECK-NEXT: umaxv {{s[0-9]+}}, [[V0]]
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%arr.load = load <16 x i32>, <16 x i32>* %arr
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%r = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> %arr.load)
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ret i32 %r
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}
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declare i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16>)
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define i16 @oversized_umin_256(<16 x i16>* nocapture readonly %arr) {
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; CHECK-LABEL: oversized_umin_256
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; CHECK: umin [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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; CHECK: uminv {{h[0-9]+}}, [[V0]]
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%arr.load = load <16 x i16>, <16 x i16>* %arr
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%r = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> %arr.load)
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ret i16 %r
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}
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declare i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32>)
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define i32 @oversized_umin_512(<16 x i32>* nocapture readonly %arr) {
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; CHECK-LABEL: oversized_umin_512
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; CHECK: umin v
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; CHECK-NEXT: umin v
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; CHECK-NEXT: umin [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
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%arr.load = load <16 x i32>, <16 x i32>* %arr
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%r = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> %arr.load)
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ret i32 %r
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}
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declare i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16>)
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define i16 @oversized_smax_256(<16 x i16>* nocapture readonly %arr) {
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; CHECK-LABEL: oversized_smax_256
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; CHECK: smax [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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; CHECK: smaxv {{h[0-9]+}}, [[V0]]
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%arr.load = load <16 x i16>, <16 x i16>* %arr
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%r = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> %arr.load)
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ret i16 %r
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}
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declare i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32>)
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define i32 @oversized_smax_512(<16 x i32>* nocapture readonly %arr) {
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; CHECK-LABEL: oversized_smax_512
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; CHECK: smax v
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; CHECK-NEXT: smax v
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; CHECK-NEXT: smax [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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; CHECK-NEXT: smaxv {{s[0-9]+}}, [[V0]]
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%arr.load = load <16 x i32>, <16 x i32>* %arr
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%r = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> %arr.load)
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ret i32 %r
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}
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declare i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16>)
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define i16 @oversized_smin_256(<16 x i16>* nocapture readonly %arr) {
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; CHECK-LABEL: oversized_smin_256
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; CHECK: smin [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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; CHECK: sminv {{h[0-9]+}}, [[V0]]
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%arr.load = load <16 x i16>, <16 x i16>* %arr
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%r = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> %arr.load)
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ret i16 %r
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}
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declare i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32>)
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define i32 @oversized_smin_512(<16 x i32>* nocapture readonly %arr) {
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; CHECK-LABEL: oversized_smin_512
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; CHECK: smin v
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; CHECK-NEXT: smin v
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; CHECK-NEXT: smin [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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; CHECK-NEXT: sminv {{s[0-9]+}}, [[V0]]
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%arr.load = load <16 x i32>, <16 x i32>* %arr
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%r = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> %arr.load)
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ret i32 %r
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}
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