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b0f83ed2ae
Summary: The following intrinsics have been extended to support brain float types: svbfloat16_t svclasta[_bf16](svbool_t pg, svbfloat16_t fallback, svbfloat16_t data) bfloat16_t svclasta[_n_bf16](svbool_t pg, bfloat16_t fallback, svbfloat16_t data) bfloat16_t svlasta[_bf16](svbool_t pg, svbfloat16_t op) svbfloat16_t svclastb[_bf16](svbool_t pg, svbfloat16_t fallback, svbfloat16_t data) bfloat16_t svclastb[_n_bf16](svbool_t pg, bfloat16_t fallback, svbfloat16_t data) bfloat16_t svlastb[_bf16](svbool_t pg, svbfloat16_t op) svbfloat16_t svdup[_n]_bf16(bfloat16_t op) svbfloat16_t svdup[_n]_bf16_m(svbfloat16_t inactive, svbool_t pg, bfloat16_t op) svbfloat16_t svdup[_n]_bf16_x(svbool_t pg, bfloat16_t op) svbfloat16_t svdup[_n]_bf16_z(svbool_t pg, bfloat16_t op) svbfloat16_t svdupq[_n]_bf16(bfloat16_t x0, bfloat16_t x1, bfloat16_t x2, bfloat16_t x3, bfloat16_t x4, bfloat16_t x5, bfloat16_t x6, bfloat16_t x7) svbfloat16_t svdupq_lane[_bf16](svbfloat16_t data, uint64_t index) svbfloat16_t svinsr[_n_bf16](svbfloat16_t op1, bfloat16_t op2) Reviewers: sdesmalen, kmclaughlin, c-rhodes, ctetreau, efriedma Subscribers: tschuett, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D82345
143 lines
4.2 KiB
LLVM
143 lines
4.2 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -mattr=+sve -asm-verbose=0 < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; WARN-NOT: warning
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;
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; Unpredicated dup instruction (which is an alias for mov):
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; * register + register,
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; * register + immediate
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;
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define <vscale x 16 x i8> @dup_i8(i8 %b) {
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; CHECK-LABEL: dup_i8:
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; CHECK: mov z0.b, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 16 x i8> @dup_imm_i8() {
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; CHECK-LABEL: dup_imm_i8:
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; CHECK: mov z0.b, #16
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 16)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @dup_i16(i16 %b) {
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; CHECK-LABEL: dup_i16:
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; CHECK: mov z0.h, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 8 x i16> @dup_imm_i16(i16 %b) {
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; CHECK-LABEL: dup_imm_i16:
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; CHECK: mov z0.h, #16
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 16)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @dup_i32(i32 %b) {
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; CHECK-LABEL: dup_i32:
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; CHECK: mov z0.s, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 4 x i32> @dup_imm_i32(i32 %b) {
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; CHECK-LABEL: dup_imm_i32:
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; CHECK: mov z0.s, #16
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 16)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @dup_i64(i64 %b) {
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; CHECK-LABEL: dup_i64:
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; CHECK: mov z0.d, x0
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %b)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 2 x i64> @dup_imm_i64(i64 %b) {
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; CHECK-LABEL: dup_imm_i64:
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; CHECK: mov z0.d, #16
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 16)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 8 x half> @dup_f16(half %b) {
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; CHECK-LABEL: dup_f16:
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; CHECK: mov z0.h, h0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %b)
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ret <vscale x 8 x half> %out
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}
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define <vscale x 8 x bfloat> @dup_bf16(bfloat %b) #0 {
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; CHECK-LABEL: dup_bf16:
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; CHECK: mov z0.h, h0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %b)
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ret <vscale x 8 x bfloat> %out
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}
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define <vscale x 8 x half> @dup_imm_f16(half %b) {
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; CHECK-LABEL: dup_imm_f16:
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; CHECK: mov z0.h, #16.00000000
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half 16.)
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ret <vscale x 8 x half> %out
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}
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define <vscale x 4 x float> @dup_f32(float %b) {
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; CHECK-LABEL: dup_f32:
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; CHECK: mov z0.s, s0
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %b)
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ret <vscale x 4 x float> %out
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}
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define <vscale x 4 x float> @dup_imm_f32(float %b) {
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; CHECK-LABEL: dup_imm_f32:
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; CHECK: mov z0.s, #16.00000000
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float 16.)
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ret <vscale x 4 x float> %out
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}
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define <vscale x 2 x double> @dup_f64(double %b) {
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; CHECK-LABEL: dup_f64:
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; CHECK: mov z0.d, d0
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %b)
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ret <vscale x 2 x double> %out
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}
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define <vscale x 2 x double> @dup_imm_f64(double %b) {
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; CHECK-LABEL: dup_imm_f64:
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; CHECK: mov z0.d, #16.00000000
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double 16.)
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ret <vscale x 2 x double> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8( i8)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64)
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declare <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half)
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declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat)
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declare <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float)
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declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double)
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; +bf16 is required for the bfloat version.
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attributes #0 = { "target-features"="+sve,+bf16" }
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