mirror of
https://github.com/RPCS3/llvm-mirror.git
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484 lines
23 KiB
C++
484 lines
23 KiB
C++
//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
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// vim:ft=cpp
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//===----------------------------------------------------------------------===//
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#include "../Target.td"
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#include "SparcV9_Reg.td"
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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class InstV9 : Instruction { // Sparc instruction baseline
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field bits<32> Inst;
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set Namespace = "V9";
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bits<2> op;
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set Inst{31-30} = op; // Top two bits are the 'op' field
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// Bit attributes specific to Sparc instructions
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bit isPasi = 0; // Does this instruction affect an alternate addr space?
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bit isDeprecated = 0; // Is this instruction deprecated?
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bit isPrivileged = 0; // Is this a privileged instruction?
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}
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#include "SparcV9_F2.td"
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#include "SparcV9_F3.td"
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#include "SparcV9_F4.td"
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//===----------------------------------------------------------------------===//
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// Instruction list...
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//
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// Section A.2: Add - p137
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def ADDr : F3_1<2, 0b000000, "add">; // add r, r, r
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def ADDi : F3_2<2, 0b000000, "add">; // add r, i, r
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def ADDccr : F3_1<2, 0b010000, "addcc">; // addcc r, r, r
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def ADDcci : F3_2<2, 0b010000, "addcc">; // addcc r, i, r
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def ADDCr : F3_1<2, 0b001000, "addC">; // addC r, r, r
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def ADDCi : F3_2<2, 0b001000, "addC">; // addC r, i, r
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def ADDCccr : F3_1<2, 0b011000, "addCcc">; // addCcc r, r, r
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def ADDCcci : F3_2<2, 0b011000, "addCcc">; // addCcc r, i, r
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// Section A.3: Branch on Integer Register with Prediction - p162
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set op2 = 0b011 in {
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def BRZ : F2_4<0b001, "brz">; // Branch on rs1 == 0
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def BRLEZ : F2_4<0b010, "brlez">; // Branch on rs1 <= 0
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def BRLZ : F2_4<0b011, "brlz">; // Branch on rs1 < 0
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def BRNZ : F2_4<0b101, "brnz">; // Branch on rs1 != 0
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def BRGZ : F2_4<0b110, "brgz">; // Branch on rs1 > 0
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def BRGEZ : F2_4<0b111, "brgez">; // Branch on rs1 >= 0
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}
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// Section A.4: p164
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set isDeprecated = 1 in {
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set op2 = 0b110 in {
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def FBA : F2_2<0b1000, "fba">; // Branch always
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def FBN : F2_2<0b0000, "fbn">; // Branch never
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def FBU : F2_2<0b0111, "fbu">; // Branch on unordered
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def FBG : F2_2<0b0110, "fbg">; // Branch >
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def FBUG : F2_2<0b0101, "fbug">; // Branch on unordered or >
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def FBL : F2_2<0b0100, "fbl">; // Branch <
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def FBUL : F2_2<0b0011, "fbul">; // Branch on unordered or <
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def FBLG : F2_2<0b0010, "fblg">; // Branch < or >
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def FBNE : F2_2<0b0001, "fbne">; // Branch !=
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def FBE : F2_2<0b1001, "fbe">; // Branch ==
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def FBUE : F2_2<0b1010, "fbue">; // Branch on unordered or ==
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def FBGE : F2_2<0b1011, "fbge">; // Branch > or ==
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def FBUGE : F2_2<0b1100, "fbuge">; // Branch unord or > or ==
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def FBLE : F2_2<0b1101, "fble">; // Branch < or ==
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def FBULE : F2_2<0b1110, "fbule">; // Branch unord or < or ==
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def FBO : F2_2<0b1111, "fbo">; // Branch on ordered
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}
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}
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// Section A.5: p167
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//set op2 = 0b101 in {
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//def FBPA : F2_3<0b1000, "fbpa">; // Branch always
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//def FBPN : F2_3<0b0000, "fbpn">; // Branch never
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//def FBPU : F2_3<0b0111, "fbpu">; // Branch on unordered
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//def FBPG : F2_3<0b0110, "fbpg">; // Branch >
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//def FBPUG : F2_3<0b0101, "fbpug">; // Branch on unordered or >
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//def FBPL : F2_3<0b0100, "fbpl">; // Branch <
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//def FBPUL : F2_3<0b0011, "fbpul">; // Branch on unordered or <
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//def FBPLG : F2_3<0b0010, "fbplg">; // Branch < or >
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//def FBPNE : F2_3<0b0001, "fbpne">; // Branch !=
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//def FBPE : F2_3<0b1001, "fbpe">; // Branch ==
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//def FBPUE : F2_3<0b1010, "fbpue">; // Branch on unordered or ==
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//def FBPGE : F2_3<0b1011, "fbpge">; // Branch > or ==
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//def FBPUGE : F2_3<0b1100, "fbpuge">; // Branch unord or > or ==
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//def FBPLE : F2_3<0b1101, "fbple">; // Branch < or ==
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//def FBPULE : F2_3<0b1110, "fbpule">; // Branch unord or < or ==
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//def FBPO : F2_3<0b1111, "fbpo">; // Branch on ordered
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//}
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// Section A.6: Branch on Integer condition codes (Bicc) - p146
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set isDeprecated = 1 in {
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set op2 = 0b010 in {
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def BA : F2_2<0b1000, "ba">; // Branch always
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def BN : F2_2<0b0000, "bn">; // Branch never
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def BNE : F2_2<0b1001, "bne">; // Branch !=
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def BE : F2_2<0b0001, "be">; // Branch ==
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def BG : F2_2<0b1010, "bg">; // Branch >
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def BLE : F2_2<0b0010, "ble">; // Branch <=
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def BGE : F2_2<0b1011, "bge">; // Branch >=
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def BL : F2_2<0b0011, "bl">; // Branch <
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def BGU : F2_2<0b1100, "bgu">; // Branch unsigned >
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def BLEU : F2_2<0b0100, "bleu">; // Branch unsigned <=
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def BCC : F2_2<0b1101, "bcc">; // Branch unsigned >=
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def BCS : F2_2<0b0101, "bcs">; // Branch unsigned <=
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def BPOS : F2_2<0b1110, "bpos">; // Branch on positive
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def BNEG : F2_2<0b0110, "bneg">; // Branch on negative
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def BVC : F2_2<0b1111, "bvc">; // Branch on overflow clear
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def BVS : F2_2<0b0111, "bvs">; // Branch on overflow set
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}
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}
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// Section A.7: Branch on integer condition codes with prediction - p148
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//set op2 = 0b001 in {
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// def BPA : F2_3<0b1000, "bpa">; // Branch always
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// def BPN : F2_3<0b0000, "bpn">; // Branch never
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// def BPNE : F2_3<0b1001, "bpne">; // Branch !=
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// def BPE : F2_3<0b0001, "bpe">; // Branch ==
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// def BPG : F2_3<0b1010, "bpg">; // Branch >
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// def BPLE : F2_3<0b0010, "bple">; // Branch <=
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// def BPGE : F2_3<0b1011, "bpge">; // Branch >=
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// def BPL : F2_3<0b0011, "bpl">; // Branch <
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// def BPGU : F2_3<0b1100, "bpgu">; // Branch unsigned >
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// def BPLEU : F2_3<0b0100, "bpleu">; // Branch unsigned <=
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// def BPCC : F2_3<0b1101, "bpcc">; // Branch unsigned >=
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// def BPCS : F2_3<0b0101, "bpcs">; // Branch unsigned <=
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// def BPPOS : F2_3<0b1110, "bppos">; // Branch on positive
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// def BPNEG : F2_3<0b0110, "bpneg">; // Branch on negative
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// def BPVC : F2_3<0b1111, "bpvc">; // Branch on overflow clear
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// def BPVS : F2_3<0b0111, "bpvs">; // Branch on overflow set
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//}
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// Section A.8: p175 - CALL - the only Format #1 instruction
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def CALL : InstV9 {
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bits<30> disp;
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set op = 1;
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set Inst{29-0} = disp;
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set Name = "call";
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set isCall = 1;
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}
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// Section A.9: Compare and Swap - p176
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// CASA/CASXA: are for alternate address spaces! Ignore them
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// Section A.10: Divide (64-bit / 32-bit) - p178
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// Not used in the Sparc backend
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//set isDeprecated = 1 in {
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//def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
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//def UDIVi : F3_2<2, 0b001110, "udiv">; // udiv r, r, i
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//def SDIVr : F3_1<2, 0b001111, "sdiv">; // sdiv r, r, r
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//def SDIVi : F3_2<2, 0b001111, "sdiv">; // sdiv r, r, i
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//def UDIVCCr : F3_1<2, 0b011110, "udivcc">; // udivcc r, r, r
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//def UDIVCCi : F3_2<2, 0b011110, "udivcc">; // udivcc r, r, i
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//def SDIVCCr : F3_1<2, 0b011111, "sdivcc">; // sdivcc r, r, r
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//def SDIVCCi : F3_2<2, 0b011111, "sdivcc">; // sdivcc r, r, i
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//}
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// Section A.11: DONE and RETRY - p181
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//set isPrivileged = 1 in {
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//def DONE : F3_18<0, "done">; // done
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//def RETRY : F3_18<1, "retry">; // retry
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//}
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// Section A.12: Floating-Point Add and Subtract - p182
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def FADDS : F3_16<2, 0b110100, 0x41, "fadds">; // fadds f, f, f
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def FADDD : F3_16<2, 0b110100, 0x42, "faddd">; // faddd f, f, f
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def FADDQ : F3_16<2, 0b110100, 0x43, "faddq">; // faddq f, f, f
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def FSUBS : F3_16<2, 0b110100, 0x45, "fsubs">; // fsubs f, f, f
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def FSUBD : F3_16<2, 0b110100, 0x46, "fsubd">; // fsubd f, f, f
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def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">; // fsubq f, f, f
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// Section A.17: Floating-Point Move - p164
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def FMOVS : F3_14<2, 0b110100, 0b000000001, "fmovs">; // fmovs r, r
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def FMOVD : F3_14<2, 0b110100, 0b000000010, "fmovs">; // fmovd r, r
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//def FMOVQ : F3_14<2, 0b110100, 0b000000011, "fmovs">; // fmovq r, r
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def FNEGS : F3_14<2, 0b110100, 0b000000101, "fnegs">; // fnegs r, r
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def FNEGD : F3_14<2, 0b110100, 0b000000110, "fnegs">; // fnegs r, r
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//def FNEGQ : F3_14<2, 0b110100, 0b000000111, "fnegs">; // fnegs r, r
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def FABSS : F3_14<2, 0b110100, 0b000001001, "fabss">; // fabss r, r
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def FABSD : F3_14<2, 0b110100, 0b000001010, "fabss">; // fabss r, r
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//def FABSQ : F3_14<2, 0b110100, 0b000001011, "fabss">; // fabss r, r
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// Section A.18: Floating-Point Multiply and Divide - p165
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def FMULS : F3_16<2, 0b110100, 0b001001001, "fmuls">; // fmuls r, r, r
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def FMULD : F3_16<2, 0b110100, 0b001001010, "fmuld">; // fmuld r, r, r
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def FMULQ : F3_16<2, 0b110100, 0b001001011, "fmulq">; // fmulq r, r, r
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def FSMULD : F3_16<2, 0b110100, 0b001101001, "fsmuld">; // fsmuls r, r, r
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def FDMULQ : F3_16<2, 0b110100, 0b001101110, "fdmulq">; // fdmuls r, r, r
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def FDIVS : F3_16<2, 0b110100, 0b001001101, "fdivs">; // fdivs r, r, r
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def FDIVD : F3_16<2, 0b110100, 0b001001110, "fdivs">; // fdivd r, r, r
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def FDIVQ : F3_16<2, 0b110100, 0b001001111, "fdivs">; // fdivq r, r, r
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// Section A.19: Floating-Point Square Root - p166
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def FSQRTS : F3_14<2, 0b110100, 0b000101001, "fsqrts">; // fsqrts r, r
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def FSQRTD : F3_14<2, 0b110100, 0b000101010, "fsqrts">; // fsqrts r, r
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def FSQRTQ : F3_14<2, 0b110100, 0b000101011, "fsqrts">; // fsqrts r, r
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// FIXME: A.20: Flush Instruction Memory - p167
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// FIXME: A.21: Flush Register Windows - p169
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// A.22: Illegal instruction Trap - p170
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// Not used
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// A.23: Implementation-Dependent Instructions - p171
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// Not used
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// Section A.24: Jump and Link - p172
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// Mimicking the Sparc's instr def...
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def JMPLCALLr : F3_1<2, 0b111000, "jmpl">; // jmpl [r+r], r
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def JMPLCALLi : F3_2<2, 0b111000, "jmpl">; // jmpl [r+i], r
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def JMPLRETr : F3_1<2, 0b111000, "jmpl">; // jmpl [r+r], r
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def JMPLRETi : F3_2<2, 0b111000, "jmpl">; // jmpl [r+i], r
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// FIXME: FCMPS, FCMPD, FCMPQ !!!
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// FIXME: FMULS, FMULD, FMULQ, ...
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// Section A.25: Load Floating-Point - p173
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def LDFr : F3_1<3, 0b100000, "ld">; // ld [r+r], r
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def LDFi : F3_2<3, 0b100000, "ld">; // ld [r+i], r
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def LDDFr : F3_1<3, 0b100011, "ldd">; // ldd [r+r], r
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def LDDFi : F3_2<3, 0b100011, "ldd">; // ldd [r+i], r
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def LDQFr : F3_1<3, 0b100010, "ldq">; // ldq [r+r], r
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def LDQFi : F3_2<3, 0b100010, "ldq">; // ldq [r+i], r
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set isDeprecated = 1 in {
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set rd = 0 in {
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def LDFSRr : F3_1<3, 0b100001, "ld">; // ld [r+r], r
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def LDFSRi : F3_2<3, 0b100001, "ld">; // ld [r+i], r
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}
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}
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set rd = 1 in {
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def LDXFSRr : F3_1<3, 0b100001, "ldx">; // ldx [r+r], r
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def LDXFSRi : F3_2<3, 0b100001, "ldx">; // ldx [r+i], r
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}
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// Section A.27: Load Integer - p178
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def LDSBr : F3_1<3, 0b001001, "ldsb">; // ldsb [r+r], r
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def LDSBi : F3_2<3, 0b001001, "ldsb">; // ldsb [r+i], r
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def LDSHr : F3_1<3, 0b001010, "ldsh">; // ldsh [r+r], r
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def LDSHi : F3_2<3, 0b001010, "ldsh">; // ldsh [r+i], r
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def LDSWr : F3_1<3, 0b001000, "ldsw">; // ldsh [r+r], r
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def LDSWi : F3_2<3, 0b001000, "ldsw">; // ldsh [r+i], r
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def LDUBr : F3_1<3, 0b000001, "ldub">; // ldub [r+r], r
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def LDUBi : F3_2<3, 0b000001, "ldub">; // ldub [r+i], r
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def LDUHr : F3_1<3, 0b000010, "lduh">; // lduh [r+r], r
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def LDUHi : F3_2<3, 0b000010, "lduh">; // lduh [r+i], r
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// synonym: LD
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def LDUWr : F3_1<3, 0b000000, "lduw">; // lduw [r+r], r
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def LDUWi : F3_2<3, 0b000000, "lduw">; // lduw [r+i], r
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// LDD should no longer be used, LDX should be used instead
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def LDXr : F3_1<3, 0b001011, "ldx">; // ldx [r+r], r
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def LDXi : F3_2<3, 0b001011, "ldx">; // ldx [r+i], r
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//set isDeprecated = 1 in {
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// def LDDr : F3_1<3, 0b000011, "ldd">; // ldd [r+r], r
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// def LDDi : F3_2<3, 0b000011, "ldd">; // ldd [r+i], r
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//}
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// Section A.31: Logical operations
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def ANDr : F3_1<2, 0b000001, "and">; // and r, r, r
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def ANDi : F3_2<2, 0b000001, "and">; // and r, r, i
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def ANDccr : F3_1<2, 0b010001, "andcc">; // andcc r, r, r
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def ANDcci : F3_2<2, 0b010001, "andcc">; // andcc r, r, i
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def ANDNr : F3_1<2, 0b000101, "andn">; // andn r, r, r
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def ANDNi : F3_2<2, 0b000101, "andn">; // andn r, r, i
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def ANDNccr : F3_1<2, 0b010101, "andncc">; // andncc r, r, r
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def ANDNcci : F3_2<2, 0b010101, "andncc">; // andncc r, r, i
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def ORr : F3_1<2, 0b000010, "or">; // or r, r, r
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def ORi : F3_2<2, 0b000010, "or">; // or r, r, i
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def ORccr : F3_1<2, 0b010010, "orcc">; // orcc r, r, r
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def ORcci : F3_2<2, 0b010010, "orcc">; // orcc r, r, i
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def ORNr : F3_1<2, 0b000110, "orn">; // orn r, r, r
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def ORNi : F3_2<2, 0b000110, "orn">; // orn r, r, i
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def ORNccr : F3_1<2, 0b010110, "orncc">; // orncc r, r, r
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def ORNcci : F3_2<2, 0b010110, "orncc">; // orncc r, r, i
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def XORr : F3_1<2, 0b000011, "xor">; // xor r, r, r
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def XORi : F3_2<2, 0b000011, "xor">; // xor r, r, i
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def XORccr : F3_1<2, 0b010011, "xorcc">; // xorcc r, r, r
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def XORcci : F3_2<2, 0b010011, "xorcc">; // xorcc r, r, i
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def XNORr : F3_1<2, 0b000111, "xnor">; // xnor r, r, r
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def XNORi : F3_2<2, 0b000111, "xnor">; // xnor r, r, i
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def XNORccr : F3_1<2, 0b010111, "xnorcc">; // xnorcc r, r, r
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def XNORcci : F3_2<2, 0b010111, "xnorcc">; // xnorcc r, r, i
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#if 0
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// Section A.33: Move Floating-Point Register on Condition (FMOVcc)
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// For integer condition codes
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def FMOVA : F4_7<2, 0b110101, 0b1000, "fmova">; // fmova r, r
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def FMOVN : F4_7<2, 0b110101, 0b0000, "fmovn">; // fmovn r, r
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def FMOVNE : F4_7<2, 0b110101, 0b1001, "fmovne">; // fmovne r, r
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def FMOVE : F4_7<2, 0b110101, 0b0000, "fmove">; // fmove r, r
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def FMOVG : F4_7<2, 0b110101, 0b1010, "fmovg">; // fmovg r, r
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def FMOVLE : F4_7<2, 0b110101, 0b0000, "fmovle">; // fmovle r, r
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def FMOVGE : F4_7<2, 0b110101, 0b1011, "fmovge">; // fmovge r, r
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def FMOVL : F4_7<2, 0b110101, 0b0011, "fmovl">; // fmovl r, r
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def FMOVGU : F4_7<2, 0b110101, 0b1100, "fmovgu">; // fmovgu r, r
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def FMOVLEU : F4_7<2, 0b110101, 0b0100, "fmovleu">; // fmovleu r, r
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def FMOVCC : F4_7<2, 0b110101, 0b1101, "fmovcc">; // fmovcc r, r
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def FMOVCS : F4_7<2, 0b110101, 0b0101, "fmovcs">; // fmovcs r, r
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def FMOVPOS : F4_7<2, 0b110101, 0b1110, "fmovpos">; // fmovpos r, r
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def FMOVNEG : F4_7<2, 0b110101, 0b0110, "fmovneg">; // fmovneg r, r
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def FMOVVC : F4_7<2, 0b110101, 0b1111, "fmovvc">; // fmovvc r, r
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def FMOVVS : F4_7<2, 0b110101, 0b0111, "fmovvs">; // fmovvs r, r
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// For floating-point condition codes
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def FMOVFA : F4_7<2, 0b110101, 0b0100, "fmovfa">; // fmovfa r, r
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def FMOVFN : F4_7<2, 0b110101, 0b0000, "fmovfn">; // fmovfa r, r
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def FMOVFU : F4_7<2, 0b110101, 0b0111, "fmovfu">; // fmovfu r, r
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def FMOVFG : F4_7<2, 0b110101, 0b0110, "fmovfg">; // fmovfg r, r
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def FMOVFUG : F4_7<2, 0b110101, 0b0101, "fmovfug">; // fmovfug r, r
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def FMOVFL : F4_7<2, 0b110101, 0b0100, "fmovfl">; // fmovfl r, r
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def FMOVFUL : F4_7<2, 0b110101, 0b0011, "fmovful">; // fmovful r, r
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def FMOVFLG : F4_7<2, 0b110101, 0b0010, "fmovflg">; // fmovflg r, r
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def FMOVFNE : F4_7<2, 0b110101, 0b0001, "fmovfne">; // fmovfne r, r
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def FMOVFE : F4_7<2, 0b110101, 0b1001, "fmovfe">; // fmovfe r, r
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def FMOVFUE : F4_7<2, 0b110101, 0b1010, "fmovfue">; // fmovfue r, r
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def FMOVGE : F4_7<2, 0b110101, 0b1011, "fmovge">; // fmovge r, r
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def FMOVFUGE : F4_7<2, 0b110101, 0b1100, "fmovfuge">; // fmovfuge r, r
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def FMOVFLE : F4_7<2, 0b110101, 0b1101, "fmovfle">; // fmovfle r, r
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def FMOVFULE : F4_7<2, 0b110101, 0b1110, "fmovfule">; // fmovfule r, r
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def FMOVFO : F4_7<2, 0b110101, 0b1111, "fmovfo">; // fmovfo r, r
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#endif
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// FIXME: Section A.34: Move F-P Register on Integer Register (FMOVr)
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// FIXME: Section A.35: Move Integer Register on Condition (MOVcc)
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// FIXME: Section A.36: Move Integer Register on Register Condition (MOVR)
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// Section A.37: Multiply and Divide (64-bit) - p199
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def MULXr : F3_1<2, 0b001001, "mulx">; // mulx r, r, r
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def SDIVXr : F3_1<2, 0b101101, "sdivx">; // mulx r, r, r
|
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def UDIVXr : F3_1<2, 0b001101, "udivx">; // mulx r, r, r
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def MULXi : F3_2<2, 0b001001, "mulx">; // mulx r, i, r
|
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def SDIVXi : F3_2<2, 0b101101, "sdivx">; // mulx r, i, r
|
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def UDIVXi : F3_2<2, 0b001101, "udivx">; // mulx r, i, r
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// Section A.38: Multiply (32-bit) - p200
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// Not used in the Sparc backend?
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//set Inst{13} = 0 in {
|
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// def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
|
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// def SMULr : F3_1<2, 0b001011, "smul">; // smul r, r, r
|
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// def UMULCCr : F3_1<2, 0b011010, "umulcc">; // mulcc r, r, r
|
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// def SMULCCr : F3_1<2, 0b011011, "smulcc">; // smulcc r, r, r
|
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//}
|
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//set Inst{13} = 1 in {
|
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// def UMULi : F3_1<2, 0b001010, "umul">; // umul r, i, r
|
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// def SMULi : F3_1<2, 0b001011, "smul">; // smul r, i, r
|
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// def UMULCCi : F3_1<2, 0b011010, "umulcc">; // umulcc r, i, r
|
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// def SMULCCi : F3_1<2, 0b011011, "smulcc">; // smulcc r, i, r
|
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//}
|
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|
|
// Section A.39: FIXME
|
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|
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// Section A.40: No operation - p204
|
|
// NOP is really a pseudo-instruction (special case of SETHI)
|
|
set op2 = 0b100 in {
|
|
set rd = 0 in {
|
|
set imm = 0 in {
|
|
def NOP : F2_1<"nop">; // nop
|
|
}
|
|
}
|
|
}
|
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|
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// Section A.41: FIXME
|
|
// Section A.42: FIXME
|
|
// Section A.43: FIXME
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|
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// Section A.44: Read State Register
|
|
// The only instr from this section currently used is RDCCR
|
|
set rs1 = 2 in {
|
|
def RDCCR : F3_17<2, 0b101000, "rd">; // rd %ccr, r
|
|
}
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|
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// Section A.45: RETURN - p216
|
|
set isReturn = 1 in {
|
|
def RETURNr : F3_3<2, 0b111001, "return">; // return
|
|
def RETURNi : F3_4<2, 0b111001, "return">; // return
|
|
}
|
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|
|
// Section A.46: SAVE and RESTORE - p217
|
|
def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
|
|
def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
|
|
def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
|
|
def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
|
|
|
|
// Section A.47: SAVED and RESTORED - p219
|
|
// Not currently used in Sparc backend
|
|
|
|
// Section A.48: SETHI - p220
|
|
set op2 = 0b100 in {
|
|
def SETHI : F2_1<"sethi">; // sethi
|
|
}
|
|
|
|
// Section A.49: Shift - p221
|
|
// uses 5 least significant bits of rs2
|
|
//set x = 0 in {
|
|
// def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
|
|
// def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r
|
|
// def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r
|
|
// def SLLXr5 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
|
|
// def SRLXr5 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
|
|
// def SRAXr5 : F3_11<2, 0b100111, "srax">; // srax r, r, r
|
|
//}
|
|
// uses 6 least significant bits of rs2
|
|
set x = 1 in {
|
|
def SLLr6 : F3_11<2, 0b100101, "sll">; // sll r, r, r
|
|
def SRLr6 : F3_11<2, 0b100110, "srl">; // srl r, r, r
|
|
def SRAr6 : F3_11<2, 0b100111, "sra">; // sra r, r, r
|
|
def SLLXr6 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
|
|
def SRLXr6 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
|
|
def SRAXr6 : F3_11<2, 0b100111, "srax">; // srax r, r, r
|
|
}
|
|
|
|
//def SLLi5 : F3_12<2, 0b100101, "sll">; // sll r, shcnt32, r
|
|
//def SRLi5 : F3_12<2, 0b100110, "srl">; // srl r, shcnt32, r
|
|
//def SRAi5 : F3_12<2, 0b100111, "sra">; // sra r, shcnt32, r
|
|
//def SLLXi5 : F3_12<2, 0b100101, "sllx">; // sllx r, shcnt32, r
|
|
//def SRLXi5 : F3_12<2, 0b100110, "srlx">; // srlx r, shcnt32, r
|
|
//def SRAXi5 : F3_12<2, 0b100111, "srax">; // srax r, shcnt32, r
|
|
|
|
def SLLi6 : F3_13<2, 0b100101, "sll">; // sll r, shcnt64, r
|
|
def SRLi6 : F3_13<2, 0b100110, "srl">; // srl r, shcnt64, r
|
|
def SRAi6 : F3_13<2, 0b100111, "sra">; // sra r, shcnt64, r
|
|
def SLLXi6 : F3_13<2, 0b100101, "sllx">; // sllx r, shcnt64, r
|
|
def SRLXi6 : F3_13<2, 0b100110, "srlx">; // srlx r, shcnt64, r
|
|
def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
|
|
|
|
// Section A.50: FIXME
|
|
|
|
// Section A.51: FIXME
|
|
|
|
// Section A.52: Store Floating-point -p225
|
|
def STFr : F3_1<3, 0b100100, "st">; // st r, [r+r]
|
|
def STFi : F3_2<3, 0b100100, "st">; // st r, [r+i]
|
|
def STDFr : F3_1<3, 0b100111, "std">; // std r, [r+r]
|
|
def STDFi : F3_2<3, 0b100111, "std">; // std r, [r+i]
|
|
// Not currently used in the Sparc backend
|
|
//def STQFr : F3_1<3, 0b100110, "stq">; // stq r, [r+r]
|
|
//def STQFi : F3_2<3, 0b100110, "stq">; // stq r, [r+i]
|
|
set isDeprecated = 1 in {
|
|
def STFSRr : F3_1<3, 0b100101, "st">; // st r, [r+r]
|
|
def STFSRi : F3_2<3, 0b100101, "st">; // st r, [r+i]
|
|
}
|
|
def STXFSRr : F3_1<3, 0b100101, "stq">; // stx r, [r+r]
|
|
def STXFSRi : F3_2<3, 0b100101, "stq">; // stx r, [r+i]
|
|
|
|
// Section A.53: FIXME
|
|
|
|
// Section A.54: Store Integer - p229
|
|
def STBr : F3_1<3, 0b000101, "stb">; // stb r, [r+r]
|
|
def STBi : F3_2<3, 0b000101, "stb">; // stb r, [r+i]
|
|
def STHr : F3_1<3, 0b000110, "stb">; // stb r, [r+r]
|
|
def STHi : F3_2<3, 0b000110, "stb">; // stb r, [r+i]
|
|
def STWr : F3_1<3, 0b000100, "stb">; // stb r, [r+r]
|
|
def STWi : F3_2<3, 0b000100, "stb">; // stb r, [r+i]
|
|
def STXr : F3_1<3, 0b001110, "stb">; // stb r, [r+r]
|
|
def STXi : F3_2<3, 0b001110, "stb">; // stb r, [r+i]
|
|
|
|
// Floating point store...
|
|
// Section A.55: FIXME
|
|
|
|
// Section A.56: Subtract - p233
|
|
def SUBr : F3_1<2, 0b000100, "sub">; // sub r, r, r
|
|
def SUBi : F3_1<2, 0b000100, "sub">; // sub r, i, r
|
|
def SUBccr : F3_1<2, 0b010100, "subcc">; // subcc r, r, r
|
|
def SUBcci : F3_1<2, 0b010100, "subcc">; // subcc r, i, r
|
|
def SUBCr : F3_1<2, 0b001100, "subc">; // subc r, r, r
|
|
def SUBCi : F3_1<2, 0b001100, "subc">; // subc r, i, r
|
|
def SUBCccr : F3_1<2, 0b011100, "subccc">; // subccc r, r, r
|
|
def SUBCcci : F3_1<2, 0b011100, "subccc">; // subccc r, i, r
|
|
|
|
// FIXME: More...?
|