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4b4c372886
This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
37 lines
1.2 KiB
LLVM
37 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck --check-prefix=SKX --check-prefix=SKX_ONLY %s
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; TODO - fix fail on KNL and move this test to avx512-insert-extract.ll
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define zeroext i8 @test_extractelement_varible_v64i1(<64 x i8> %a, <64 x i8> %b, i32 %index) {
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; SKX-LABEL: test_extractelement_varible_v64i1:
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; SKX: ## BB#0:
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; SKX-NEXT: pushq %rbp
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; SKX-NEXT: Lcfi0:
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; SKX-NEXT: .cfi_def_cfa_offset 16
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; SKX-NEXT: Lcfi1:
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; SKX-NEXT: .cfi_offset %rbp, -16
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; SKX-NEXT: movq %rsp, %rbp
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; SKX-NEXT: Lcfi2:
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; SKX-NEXT: .cfi_def_cfa_register %rbp
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; SKX-NEXT: andq $-64, %rsp
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; SKX-NEXT: subq $128, %rsp
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; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
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; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0
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; SKX-NEXT: vpmovm2b %k0, %zmm0
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; SKX-NEXT: vmovdqu8 %zmm0, (%rsp)
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; SKX-NEXT: andl $63, %edi
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; SKX-NEXT: movq %rsp, %rax
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; SKX-NEXT: movzbl (%rdi,%rax), %eax
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; SKX-NEXT: andl $1, %eax
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; SKX-NEXT: movq %rbp, %rsp
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; SKX-NEXT: popq %rbp
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; SKX-NEXT: vzeroupper
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; SKX-NEXT: retq
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%t1 = icmp ugt <64 x i8> %a, %b
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%t2 = extractelement <64 x i1> %t1, i32 %index
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%res = zext i1 %t2 to i8
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ret i8 %res
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}
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