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4b4c372886
This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 llvm-svn: 303421
48 lines
1.5 KiB
LLVM
48 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx | FileCheck %s
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@c = external global i8, align 1
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; Function Attrs: noinline nounwind
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define void @_Z1av() {
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; CHECK-LABEL: _Z1av:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: subl $2, %esp
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; CHECK-NEXT: .Lcfi0:
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; CHECK-NEXT: .cfi_def_cfa_offset 6
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: movb %al, %cl
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; CHECK-NEXT: movb c, %dl
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; CHECK-NEXT: xorb $-1, %dl
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; CHECK-NEXT: testb $1, %dl
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; CHECK-NEXT: movb %cl, (%esp) # 1-byte Spill
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; CHECK-NEXT: jne .LBB0_1
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; CHECK-NEXT: jmp .LBB0_2
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; CHECK-NEXT: .LBB0_1: # %land.rhs
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: movb %al, %cl
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; CHECK-NEXT: movb %cl, (%esp) # 1-byte Spill
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; CHECK-NEXT: jmp .LBB0_2
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; CHECK-NEXT: .LBB0_2: # %land.end
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; CHECK-NEXT: movb (%esp), %al # 1-byte Reload
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; CHECK-NEXT: andb $1, %al
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; CHECK-NEXT: movb %al, {{[0-9]+}}(%esp)
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; CHECK-NEXT: addl $2, %esp
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; CHECK-NEXT: retl
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entry:
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%b = alloca i8, align 1
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%0 = load i8, i8* @c, align 1
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%tobool = trunc i8 %0 to i1
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%lnot = xor i1 %tobool, true
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br i1 %lnot, label %land.rhs, label %land.end
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land.rhs: ; preds = %entry
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br label %land.end
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land.end: ; preds = %land.rhs, %entry
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%1 = phi i1 [ false, %entry ], [ false, %land.rhs ]
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%conv = zext i1 %1 to i8
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store i8 %conv, i8* %b, align 1
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ret void
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}
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