mirror of
https://github.com/RPCS3/llvm-mirror.git
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7c215e1404
Summary: The patch tries to fold sqrt/sdiv test node, i.g FTSQRT, XVTDIVDP, and the branch, i.e br_cc if they meet these patterns: (br_cc seteq, (truncateToi1 SWTestOp), 0) -> (BCC PRED_NU, SWTestOp) (br_cc seteq, (and SWTestOp, 2), 0) -> (BCC PRED_NE, SWTestOp) (br_cc seteq, (and SWTestOp, 4), 0) -> (BCC PRED_LE, SWTestOp) (br_cc seteq, (and SWTestOp, 8), 0) -> (BCC PRED_GE, SWTestOp) (br_cc setne, (truncateToi1 SWTestOp), 0) -> (BCC PRED_UN, SWTestOp) (br_cc setne, (and SWTestOp, 2), 0) -> (BCC PRED_EQ, SWTestOp) (br_cc setne, (and SWTestOp, 4), 0) -> (BCC PRED_GT, SWTestOp) (br_cc setne, (and SWTestOp, 8), 0) -> (BCC PRED_LT, SWTestOp) Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D94054
205 lines
6.5 KiB
LLVM
205 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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@val = external local_unnamed_addr global i32, align 4
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declare i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double>)
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define dso_local signext i32 @xvtsqrtdp_and_1_eq(<2 x double> %input) {
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; CHECK-LABEL: xvtsqrtdp_and_1_eq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtsqrtdp cr0, v2
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; CHECK-NEXT: bnu cr0, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-NEXT: li r4, 100
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; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-NEXT: stw r4, 0(r3)
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; CHECK-NEXT: .LBB0_2: # %if.end
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
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%1 = and i32 %0, 1
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%cmp.not = icmp eq i32 %1, 0
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br i1 %cmp.not, label %if.end, label %if.then
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if.then: ; preds = %entry
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store i32 100, i32* @val, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 1
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}
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define dso_local signext i32 @xvtsqrtdp_and_2_eq(<2 x double> %input) {
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; CHECK-LABEL: xvtsqrtdp_and_2_eq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtsqrtdp cr0, v2
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; CHECK-NEXT: bne cr0, .LBB1_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-NEXT: li r4, 100
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; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-NEXT: stw r4, 0(r3)
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; CHECK-NEXT: .LBB1_2: # %if.end
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
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%1 = and i32 %0, 2
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%cmp.not = icmp eq i32 %1, 0
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br i1 %cmp.not, label %if.end, label %if.then
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if.then: ; preds = %entry
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store i32 100, i32* @val, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 1
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}
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define dso_local signext i32 @xvtsqrtdp_and_4_eq(<2 x double> %input) {
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; CHECK-LABEL: xvtsqrtdp_and_4_eq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtsqrtdp cr0, v2
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; CHECK-NEXT: ble cr0, .LBB2_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-NEXT: li r4, 100
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; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-NEXT: stw r4, 0(r3)
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; CHECK-NEXT: .LBB2_2: # %if.end
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
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%1 = and i32 %0, 4
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%cmp.not = icmp eq i32 %1, 0
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br i1 %cmp.not, label %if.end, label %if.then
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if.then: ; preds = %entry
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store i32 100, i32* @val, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 1
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}
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define dso_local signext i32 @xvtsqrtdp_and_8_eq(<2 x double> %input) {
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; CHECK-LABEL: xvtsqrtdp_and_8_eq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtsqrtdp cr0, v2
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; CHECK-NEXT: bge cr0, .LBB3_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-NEXT: li r4, 100
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; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-NEXT: stw r4, 0(r3)
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; CHECK-NEXT: .LBB3_2: # %if.end
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
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%1 = and i32 %0, 8
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%cmp.not = icmp eq i32 %1, 0
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br i1 %cmp.not, label %if.end, label %if.then
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if.then: ; preds = %entry
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store i32 100, i32* @val, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 1
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}
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define dso_local signext i32 @xvtsqrtdp_and_1_ne(<2 x double> %input) {
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; CHECK-LABEL: xvtsqrtdp_and_1_ne:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtsqrtdp cr0, v2
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; CHECK-NEXT: bun cr0, .LBB4_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-NEXT: li r4, 100
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; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-NEXT: stw r4, 0(r3)
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; CHECK-NEXT: .LBB4_2: # %if.end
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
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%1 = and i32 %0, 1
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%cmp.not = icmp ne i32 %1, 0
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br i1 %cmp.not, label %if.end, label %if.then
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if.then: ; preds = %entry
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store i32 100, i32* @val, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 1
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}
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define dso_local signext i32 @xvtsqrtdp_and_2_ne(<2 x double> %input) {
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; CHECK-LABEL: xvtsqrtdp_and_2_ne:
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; CHECK: # %bb.0: # %if.end
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: blr
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if.end: ; preds = %if.then, %entry
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ret i32 1
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}
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define dso_local signext i32 @xvtsqrtdp_and_4_ne(<2 x double> %input) {
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; CHECK-LABEL: xvtsqrtdp_and_4_ne:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtsqrtdp cr0, v2
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; CHECK-NEXT: bgt cr0, .LBB6_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-NEXT: li r4, 100
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; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-NEXT: stw r4, 0(r3)
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; CHECK-NEXT: .LBB6_2: # %if.end
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
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%1 = and i32 %0, 4
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%cmp.not = icmp ne i32 %1, 0
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br i1 %cmp.not, label %if.end, label %if.then
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if.then: ; preds = %entry
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store i32 100, i32* @val, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 1
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}
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define dso_local signext i32 @xvtsqrtdp_and_8_ne(<2 x double> %input) {
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; CHECK-LABEL: xvtsqrtdp_and_8_ne:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtsqrtdp cr0, v2
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; CHECK-NEXT: blt cr0, .LBB7_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-NEXT: li r4, 100
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; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-NEXT: stw r4, 0(r3)
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; CHECK-NEXT: .LBB7_2: # %if.end
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
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%1 = and i32 %0, 8
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%cmp.not = icmp ne i32 %1, 0
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br i1 %cmp.not, label %if.end, label %if.then
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if.then: ; preds = %entry
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store i32 100, i32* @val, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 1
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}
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