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a538a3723b
Summary: How we copying the CRRC to GRC is using a single MFOCRF to copy the contents of CR field n (CR bits 4×n+32:4×n+35) into bits 4×n+32:4×n+35 of register GRC. That’s not correct because we expect the value of destination register equals to source so we have to put the the contents of CR field in the lowest 4 bits. This patch adds a RLWINM after MFOCRF to achieve that. The problem came up when adding builtins for xvtdivdp, xvtdivsp, xvtsqrtdp, xvtsqrtsp, as posted in D88278. We need to move the outputs (in CR register) to GRC. However outputs of these instructions may not in a fixed CR# register, so we can’t directly add a rotation instruction in the .td patterns, but need to wait until the CR register is determined. Then we confirmed this should be a bug in POST-RA PSEUDO PASS. Reviewed By: nemanjai, shchenz Differential Revision: https://reviews.llvm.org/D88274
31 lines
855 B
LLVM
31 lines
855 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \
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; RUN: -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s
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define dso_local void @main() #0 {
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; CHECK-LABEL: main:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: tabortwci. 0, 3, 0
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; CHECK-NEXT: mfocrf 3, 128
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; CHECK-NEXT: srwi 3, 3, 28
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; CHECK-NEXT: rlwinm. 3, 3, 31, 30, 31
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; CHECK-NEXT: beqlr+ 0
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; CHECK-NEXT: # %bb.1:
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%1 = call i64 @llvm.ppc.ttest() #1
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%2 = lshr i64 %1, 1
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%3 = and i64 %2, 3
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%4 = icmp eq i64 %3, 0
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br i1 %4, label %5, label %6
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5: ; preds = %0
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ret void
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6: ; preds = %0
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unreachable
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}
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; Function Attrs: nounwind
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declare i64 @llvm.ppc.ttest() #1
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