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1dcd9f1f31
This patch add the ISD::LRINT and ISD::LLRINT along with new intrinsics. The changes are straightforward as for other floating-point rounding functions, with just some adjustments required to handle the return value being an interger. The idea is to optimize lrint/llrint generation for AArch64 in a subsequent patch. Current semantic is just route it to libm symbol. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D62017 llvm-svn: 361875
57 lines
1.3 KiB
LLVM
57 lines
1.3 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc64le | FileCheck %s
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; CHECK-LABEL: testmsws:
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; CHECK: bl lrintf
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define signext i32 @testmsws(float %x) {
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entry:
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%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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; CHECK-LABEL: testmsxs:
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; CHECK: bl lrintf
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define i64 @testmsxs(float %x) {
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entry:
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%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
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ret i64 %0
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}
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; CHECK-LABEL: testmswd:
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; CHECK: bl lrint
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define signext i32 @testmswd(double %x) {
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entry:
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%0 = tail call i64 @llvm.lrint.i64.f64(double %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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; CHECK-LABEL: testmsxd:
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; CHECK: bl lrint
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define i64 @testmsxd(double %x) {
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entry:
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%0 = tail call i64 @llvm.lrint.i64.f64(double %x)
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ret i64 %0
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}
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; CHECK-LABEL: testmswl:
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; CHECK: bl lrintl
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define signext i32 @testmswl(ppc_fp128 %x) {
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entry:
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%0 = tail call i64 @llvm.lrint.i64.ppcf128(ppc_fp128 %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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; CHECK-LABEL: testmsll:
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; CHECK: bl lrintl
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define i64 @testmsll(ppc_fp128 %x) {
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entry:
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%0 = tail call i64 @llvm.lrint.i64.ppcf128(ppc_fp128 %x)
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ret i64 %0
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}
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declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
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declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
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declare i64 @llvm.lrint.i64.ppcf128(ppc_fp128) nounwind readnone
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