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b378d94cb6
This patch implements the set boolean condition instructions introduced in POWER10. The set boolean condition instructions (set[n]bc[r]) are used during the following situations: - sign/zero/any extending i1 to an i32 or i64, - reg+reg, reg+imm or floating point comparisons being sign/zero extended to i32 or i64, - spilling CR bits (using the setnbc instruction) Differential Revision: https://reviews.llvm.org/D87705
242 lines
8.2 KiB
LLVM
242 lines
8.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-BE
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; This test case tests spilling the CR LT bit on Power10. On Power10, this is
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; achieved by setb %reg, %CRREG (lt bit) -> stw %reg, $FI instead of:
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; mfocrf %reg, %CRREG -> rlwinm %reg1, %reg, $SH, 0, 0 -> stw %reg1, $FI.
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; Without fine-grained control over clobbering individual CR bits,
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; it is difficult to produce a concise test case that will ensure a specific
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; bit of any CR field is spilled. We need to test the spilling of a CR bit
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; other than the LT bit. Hence this test case is rather complex.
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%0 = type { %1 }
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%1 = type { %0*, %0*, %0*, i32 }
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@call_1 = external dso_local unnamed_addr global i32, align 4
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declare %0* @call_2() local_unnamed_addr
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declare i32 @call_3() local_unnamed_addr
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declare void @call_4() local_unnamed_addr
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define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
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; CHECK-LABEL: P10_Spill_CR_LT:
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; CHECK: .localentry P10_Spill_CR_LT, 1
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; CHECK-NEXT: # %bb.0: # %bb
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: mfcr r12
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stw r12, 8(r1)
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; CHECK-NEXT: stdu r1, -80(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 80
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r30, -16
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; CHECK-NEXT: .cfi_offset cr2, 8
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; CHECK-NEXT: .cfi_offset cr3, 8
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; CHECK-NEXT: .cfi_offset cr4, 8
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; CHECK-NEXT: std r30, 64(r1) # 8-byte Folded Spill
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; CHECK-NEXT: bl call_2@notoc
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; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_13
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; CHECK-NEXT: # %bb.1: # %bb
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; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_14
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; CHECK-NEXT: # %bb.2: # %bb4
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; CHECK-NEXT: cmpdi cr3, r3, 0
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; CHECK-NEXT: # implicit-def: $r30
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; CHECK-NEXT: crnot 4*cr5+lt, 4*cr3+eq
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; CHECK-NEXT: setnbc r3, 4*cr5+lt
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; CHECK-NEXT: stw r3, 60(r1)
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; CHECK-NEXT: lwz r3, 0(r3)
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; CHECK-NEXT: cmpwi cr4, r3, 0
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_3: # %bb12
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; CHECK-NEXT: #
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; CHECK-NEXT: bl call_3@notoc
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; CHECK-NEXT: cmpwi r3, 1
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; CHECK-NEXT: crnand 4*cr5+lt, eq, 4*cr4+gt
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; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_8
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; CHECK-NEXT: # %bb.4: # %bb23
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; CHECK-NEXT: #
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; CHECK-NEXT: plwz r3, call_1@PCREL(0), 1
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; CHECK-NEXT: cmplwi r3, 0
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; CHECK-NEXT: bne- cr0, .LBB0_10
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; CHECK-NEXT: # %bb.5: # %bb30
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; CHECK-NEXT: #
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; CHECK-NEXT: bc 12, 4*cr3+eq, .LBB0_9
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; CHECK-NEXT: # %bb.6: # %bb32
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; CHECK-NEXT: #
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; CHECK-NEXT: rlwinm r30, r30, 0, 24, 22
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; CHECK-NEXT: andi. r3, r30, 2
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; CHECK-NEXT: mcrf cr2, cr0
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; CHECK-NEXT: bl call_4@notoc
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; CHECK-NEXT: beq+ cr2, .LBB0_3
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; CHECK-NEXT: # %bb.7: # %bb37
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; CHECK-NEXT: .LBB0_8: # %bb22
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; CHECK-NEXT: .LBB0_9: # %bb35
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; CHECK-NEXT: .LBB0_10: # %bb27
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; CHECK-NEXT: lwz r4, 60(r1)
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; CHECK-NEXT: # implicit-def: $cr5lt
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; CHECK-NEXT: mfocrf r3, 4
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; CHECK-NEXT: rlwimi r3, r4, 12, 20, 20
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; CHECK-NEXT: mtocrf 4, r3
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; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_12
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; CHECK-NEXT: # %bb.11: # %bb28
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; CHECK-NEXT: .LBB0_12: # %bb29
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; CHECK-NEXT: .LBB0_13: # %bb3
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; CHECK-NEXT: .LBB0_14: # %bb2
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;
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; CHECK-BE-LABEL: P10_Spill_CR_LT:
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; CHECK-BE: # %bb.0: # %bb
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; CHECK-BE-NEXT: mflr r0
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; CHECK-BE-NEXT: mfcr r12
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; CHECK-BE-NEXT: std r0, 16(r1)
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; CHECK-BE-NEXT: stw r12, 8(r1)
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; CHECK-BE-NEXT: stdu r1, -160(r1)
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; CHECK-BE-NEXT: .cfi_def_cfa_offset 160
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; CHECK-BE-NEXT: .cfi_offset lr, 16
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; CHECK-BE-NEXT: .cfi_offset r29, -24
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; CHECK-BE-NEXT: .cfi_offset r30, -16
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; CHECK-BE-NEXT: .cfi_offset cr2, 8
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; CHECK-BE-NEXT: .cfi_offset cr2, 8
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; CHECK-BE-NEXT: .cfi_offset cr2, 8
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; CHECK-BE-NEXT: std r29, 136(r1) # 8-byte Folded Spill
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; CHECK-BE-NEXT: std r30, 144(r1) # 8-byte Folded Spill
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; CHECK-BE-NEXT: bl call_2
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; CHECK-BE-NEXT: nop
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; CHECK-BE-NEXT: bc 12, 4*cr5+lt, .LBB0_13
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; CHECK-BE-NEXT: # %bb.1: # %bb
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; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_14
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; CHECK-BE-NEXT: # %bb.2: # %bb4
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; CHECK-BE-NEXT: cmpdi cr3, r3, 0
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; CHECK-BE-NEXT: addis r30, r2, call_1@toc@ha
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; CHECK-BE-NEXT: # implicit-def: $r29
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; CHECK-BE-NEXT: crnot 4*cr5+lt, 4*cr3+eq
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; CHECK-BE-NEXT: setnbc r3, 4*cr5+lt
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; CHECK-BE-NEXT: stw r3, 132(r1)
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; CHECK-BE-NEXT: lwz r3, 0(r3)
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; CHECK-BE-NEXT: cmpwi cr4, r3, 0
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; CHECK-BE-NEXT: .p2align 4
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; CHECK-BE-NEXT: .LBB0_3: # %bb12
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; CHECK-BE-NEXT: #
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; CHECK-BE-NEXT: bl call_3
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; CHECK-BE-NEXT: nop
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; CHECK-BE-NEXT: cmpwi r3, 1
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; CHECK-BE-NEXT: crnand 4*cr5+lt, eq, 4*cr4+gt
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; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_8
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; CHECK-BE-NEXT: # %bb.4: # %bb23
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; CHECK-BE-NEXT: #
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; CHECK-BE-NEXT: lwz r3, call_1@toc@l(r30)
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; CHECK-BE-NEXT: cmplwi r3, 0
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; CHECK-BE-NEXT: bne- cr0, .LBB0_10
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; CHECK-BE-NEXT: # %bb.5: # %bb30
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; CHECK-BE-NEXT: #
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; CHECK-BE-NEXT: bc 12, 4*cr3+eq, .LBB0_9
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; CHECK-BE-NEXT: # %bb.6: # %bb32
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; CHECK-BE-NEXT: #
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; CHECK-BE-NEXT: rlwinm r29, r29, 0, 24, 22
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; CHECK-BE-NEXT: andi. r3, r29, 2
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; CHECK-BE-NEXT: mcrf cr2, cr0
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; CHECK-BE-NEXT: bl call_4
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; CHECK-BE-NEXT: nop
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; CHECK-BE-NEXT: beq+ cr2, .LBB0_3
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; CHECK-BE-NEXT: # %bb.7: # %bb37
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; CHECK-BE-NEXT: .LBB0_8: # %bb22
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; CHECK-BE-NEXT: .LBB0_9: # %bb35
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; CHECK-BE-NEXT: .LBB0_10: # %bb27
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; CHECK-BE-NEXT: lwz r4, 132(r1)
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; CHECK-BE-NEXT: # implicit-def: $cr5lt
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; CHECK-BE-NEXT: mfocrf r3, 4
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; CHECK-BE-NEXT: rlwimi r3, r4, 12, 20, 20
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; CHECK-BE-NEXT: mtocrf 4, r3
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; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_12
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; CHECK-BE-NEXT: # %bb.11: # %bb28
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; CHECK-BE-NEXT: .LBB0_12: # %bb29
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; CHECK-BE-NEXT: .LBB0_13: # %bb3
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; CHECK-BE-NEXT: .LBB0_14: # %bb2
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bb:
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%tmp = tail call %0* @call_2()
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%tmp1 = icmp ne %0* %tmp, null
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switch i32 undef, label %bb4 [
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i32 3, label %bb2
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i32 2, label %bb3
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]
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bb2: ; preds = %bb
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unreachable
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bb3: ; preds = %bb
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unreachable
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bb4: ; preds = %bb
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%tmp5 = load i64, i64* undef, align 8
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%tmp6 = trunc i64 %tmp5 to i32
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%tmp7 = add i32 0, %tmp6
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%tmp8 = icmp sgt i32 %tmp7, 0
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%tmp9 = icmp eq i8 0, 0
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%tmp10 = zext i1 %tmp9 to i32
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%tmp11 = icmp eq %0* %tmp, null
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br label %bb12
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bb12: ; preds = %bb38, %bb4
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%tmp13 = phi i32 [ %tmp10, %bb4 ], [ undef, %bb38 ]
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%tmp14 = phi i32 [ undef, %bb4 ], [ %tmp17, %bb38 ]
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%tmp15 = icmp ne i32 %tmp13, 0
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%tmp16 = and i32 %tmp14, -257
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%tmp17 = select i1 %tmp15, i32 %tmp16, i32 undef
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br label %bb18
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bb18: ; preds = %bb12
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%tmp19 = call zeroext i32 @call_3()
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%tmp20 = icmp eq i32 %tmp19, 1
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%tmp21 = and i1 %tmp8, %tmp20
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br i1 %tmp21, label %bb22, label %bb23
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bb22: ; preds = %bb18
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unreachable
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bb23: ; preds = %bb18
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br label %bb24
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bb24: ; preds = %bb23
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%tmp25 = load i32, i32* @call_1, align 4
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%tmp26 = icmp eq i32 %tmp25, 0
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br i1 %tmp26, label %bb30, label %bb27
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bb27: ; preds = %bb24
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br i1 %tmp1, label %bb28, label %bb29
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bb28: ; preds = %bb27
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unreachable
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bb29: ; preds = %bb27
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unreachable
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bb30: ; preds = %bb24
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br label %bb31
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bb31: ; preds = %bb30
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br i1 %tmp11, label %bb35, label %bb32
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bb32: ; preds = %bb31
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%tmp33 = and i32 %tmp17, 2
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%tmp34 = icmp eq i32 %tmp33, 0
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call void @call_4()
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br label %bb36
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bb35: ; preds = %bb31
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unreachable
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bb36: ; preds = %bb32
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br i1 %tmp34, label %bb38, label %bb37
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bb37: ; preds = %bb36
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unreachable
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bb38: ; preds = %bb36
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br label %bb12
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}
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