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https://github.com/RPCS3/llvm-mirror.git
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999d7986df
This patch implements builtins for the following prototypes for the VSX Permute Control Vector Generate with Mask Instructions: vector unsigned char vec_genpcvm (vector unsigned char, const int); vector unsigned short vec_genpcvm (vector unsigned short, const int); vector unsigned int vec_genpcvm (vector unsigned int, const int); vector unsigned long long vec_genpcvm (vector unsigned long long, const int); Differential Revision: https://reviews.llvm.org/D81774
52 lines
1.6 KiB
LLVM
52 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; These test cases aim to test the VSX PCV Generate Operations on Power10.
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declare <16 x i8> @llvm.ppc.vsx.xxgenpcvbm(<16 x i8>, i32)
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declare <8 x i16> @llvm.ppc.vsx.xxgenpcvhm(<8 x i16>, i32)
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declare <4 x i32> @llvm.ppc.vsx.xxgenpcvwm(<4 x i32>, i32)
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declare <2 x i64> @llvm.ppc.vsx.xxgenpcvdm(<2 x i64>, i32)
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define <16 x i8> @test_xxgenpcvbm(<16 x i8> %a) {
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; CHECK-LABEL: test_xxgenpcvbm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxgenpcvbm v2, v2, 1
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; CHECK-NEXT: blr
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entry:
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%gen = tail call <16 x i8> @llvm.ppc.vsx.xxgenpcvbm(<16 x i8> %a, i32 1)
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ret <16 x i8> %gen
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}
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define <8 x i16> @test_xxgenpcvhm(<8 x i16> %a) {
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; CHECK-LABEL: test_xxgenpcvhm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxgenpcvhm v2, v2, 1
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; CHECK-NEXT: blr
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entry:
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%gen = tail call <8 x i16> @llvm.ppc.vsx.xxgenpcvhm(<8 x i16> %a, i32 1)
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ret <8 x i16> %gen
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}
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define <4 x i32> @test_xxgenpcvwm(<4 x i32> %a) {
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; CHECK-LABEL: test_xxgenpcvwm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxgenpcvwm v2, v2, 1
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; CHECK-NEXT: blr
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entry:
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%gen = tail call <4 x i32> @llvm.ppc.vsx.xxgenpcvwm(<4 x i32> %a, i32 1)
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ret <4 x i32> %gen
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}
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define <2 x i64> @test_xxgenpcvdm(<2 x i64> %a) {
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; CHECK-LABEL: test_xxgenpcvdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxgenpcvdm v2, v2, 1
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; CHECK-NEXT: blr
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entry:
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%gen = tail call <2 x i64> @llvm.ppc.vsx.xxgenpcvdm(<2 x i64> %a, i32 1)
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ret <2 x i64> %gen
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}
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