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35402c17d4
This patch will address using the xscpsgndp instruction to copy floating point scalar registers instead of the xxlor (specifically XXLORf) instruction that is currently used. Additionally, this patch of utilizing xscpsgndp will apply to P9, while pre-P9 will still use xxlor. Patch by amyk Differential Revision: https://reviews.llvm.org/D50004 llvm-svn: 340643
49 lines
1.4 KiB
LLVM
49 lines
1.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck -check-prefix=CHECK-BE %s
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; Function Attrs: norecurse nounwind readnone
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define double @cp_fp1(<2 x double> %v) {
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; CHECK-LABEL: cp_fp1:
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; CHECK: xscpsgndp f1, v2, v2
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; CHECK: blr
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; CHECK-BE-LABEL: cp_fp1:
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; CHECK-BE: xxswapd vs1, v2
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; CHECK-BE: blr
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entry:
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%vecext = extractelement <2 x double> %v, i32 1
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ret double %vecext
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}
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; Function Attrs: norecurse nounwind readnone
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define double @cp_fp2(<2 x double> %v) {
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; CHECK-LABEL: cp_fp2:
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; CHECK: xxswapd vs1, v2
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; CHECK: blr
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; CHECK-BE-LABEL: cp_fp2:
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; CHECK-BE: xscpsgndp f1, v2, v2
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; CHECK-BE: blr
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entry:
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%vecext = extractelement <2 x double> %v, i32 0
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ret double %vecext
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}
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; Function Attrs: norecurse nounwind readnone
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define <2 x double> @cp_fp3(double %v) {
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; CHECK-LABEL: cp_fp3:
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; CHECK: xxspltd v2, vs1, 0
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; CHECK: blr
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; CHECK-BE-LABEL: cp_fp3:
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; CHECK-BE: xscpsgndp v2, f1, f1
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; CHECK-BE: blr
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entry:
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%vecins = insertelement <2 x double> undef, double %v, i32 0
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ret <2 x double> %vecins
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}
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