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72298af4c5
In `PPCTargetLowering::DAGCombineTruncBoolExt`, when checking if it's correct to perform the transformation for non-sign comparison, as the comment says
```
// This is neither a signed nor an unsigned comparison, just make sure
// that the high bits are equal.
```
Origin check
```
if (Op1Known.Zero != Op2Known.Zero || Op1Known.One != Op2Known.One)
return SDValue();
```
is not strong enough. For example,
```
Op1Known = 111x000x;
Op2Known = 111x000x;
```
Bit 4, besides bit 0, is still unknown and affects the final result.
This patch fixes https://bugs.llvm.org/show_bug.cgi?id=48388.
Reviewed By: nemanjai, #powerpc
Differential Revision: https://reviews.llvm.org/D93092
42 lines
1.3 KiB
LLVM
42 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le -ppc-asm-full-reg-names \
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; RUN: < %s | FileCheck %s
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define i64 @julia_div_i64(i64 %0, i64 %1) local_unnamed_addr #0 {
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; CHECK-LABEL: julia_div_i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: divd r6, r3, r4
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; CHECK-NEXT: lis r5, -1592
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; CHECK-NEXT: ori r7, r5, 21321
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; CHECK-NEXT: ori r5, r5, 65519
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; CHECK-NEXT: cmpdi r3, 0
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; CHECK-NEXT: rldic r7, r7, 4, 17
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; CHECK-NEXT: rldic r5, r5, 4, 17
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; CHECK-NEXT: iselgt r9, r5, r7
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; CHECK-NEXT: cmpdi r4, 0
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; CHECK-NEXT: mulld r8, r6, r4
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; CHECK-NEXT: iselgt r4, r5, r7
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; CHECK-NEXT: xor r4, r9, r4
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; CHECK-NEXT: cntlzd r4, r4
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; CHECK-NEXT: rldicl r4, r4, 58, 63
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; CHECK-NEXT: xor r3, r8, r3
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; CHECK-NEXT: addic r5, r3, -1
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; CHECK-NEXT: subfe r3, r5, r3
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; CHECK-NEXT: and r3, r4, r3
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; CHECK-NEXT: add r3, r6, r3
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; CHECK-NEXT: blr
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entry:
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%2 = sdiv i64 %0, %1
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%3 = icmp sgt i64 %0, 0
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%4 = icmp sgt i64 %1, 0
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%5 = select i1 %3, i64 140735820070640, i64 140735819363472
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%6 = select i1 %4, i64 140735820070640, i64 140735819363472
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%7 = icmp eq i64 %5, %6
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%8 = mul i64 %2, %1
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%9 = icmp ne i64 %8, %0
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%10 = and i1 %7, %9
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%11 = zext i1 %10 to i64
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%12 = add i64 %2, %11
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ret i64 %12
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}
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