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d2bd14842f
The "dead" markings allow existing target-independent optimizations, like MachineSink, to trigger more frequently. The CPSR defs would have eventually been marked dead by LiveVariables, so this only affects optimizations before regalloc. The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible with this change: the transform adds a use to an otherwise dead def of CPSR. This is covered by existing regression tests. thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the generated code; I'll fix it in D53452. Differential Revision: https://reviews.llvm.org/D53453 llvm-svn: 345420
191 lines
5.2 KiB
LLVM
191 lines
5.2 KiB
LLVM
; RUN: opt -consthoist -S %s -o - | FileCheck %s --check-prefix=OPT
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; RUN: opt -consthoist -S -consthoist-min-num-to-rebase=1 %s -o - | FileCheck %s --check-prefix=OPT --check-prefix=OPT-1
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; RUN: opt -consthoist -S -consthoist-min-num-to-rebase=2 %s -o - | FileCheck %s --check-prefix=OPT --check-prefix=OPT-2
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; RUN: opt -consthoist -S -consthoist-min-num-to-rebase=3 %s -o - | FileCheck %s --check-prefix=OPT --check-prefix=OPT-3
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; RUN: llc -consthoist-min-num-to-rebase=2 %s -o - | FileCheck %s --check-prefix=LLC
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m-none-unknown-musleabi"
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; Test that constant 0 and 1 of i1 type is NOT hoisted due low
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; materializing cost.
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; OPT-LABEL: avalon
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; OPT: bb1:
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; OPT: store i1 true
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; OPT: bb2:
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; OPT: store i1 false
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; OPT: bb3:
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; OPT: store i1 false
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; OPT: store i1 false
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; OPT-NOT: add
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; LLC-LABEL: avalon
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; LLC-DAG: movs r{{[0-9]+}}, #0
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; LLC-DAG: movs r{{[0-9]+}}, #1
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; LLC-NOT: add
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@global = local_unnamed_addr global i1 undef, align 1
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@global.0 = local_unnamed_addr global i1 undef, align 1
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define void @avalon() #0 {
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bb:
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switch i8 undef, label %bb5 [
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i8 0, label %bb1
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i8 -1, label %bb2
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i8 1, label %bb3
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]
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bb1:
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store i1 1, i1* @global, align 1
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unreachable
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bb2:
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store i1 0, i1* @global, align 1
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unreachable
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bb3:
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store i1 0, i1* @global.0, align 1
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store i1 0, i1* @global, align 1
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unreachable
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bb5:
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ret void
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}
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; Test that for i8 type, constant -1 is not rebased since it's the only
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; dependent of base constant -2.
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; This test is also covered by r342898, see
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; test/CodeGen/Thumb/consthoist-imm8-costs-1.ll
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; OPT-2-LABEL: barney
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; OPT-2: bb1:
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; OPT-2: store i8 -1
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; OPT-2: bb2:
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; OPT-2: store i8 -2
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; OPT-2: bb3:
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; OPT-2: store i8 -2
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; OPT-2: store i8 -2
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; OPT-2-NOT: add
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; LLC-LABEL: barney
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; LLC-DAG: movs r{{[0-9]+}}, #254
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; LLC-DAG: movs r{{[0-9]+}}, #255
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; LLC-NOT: mvn
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; LLC-NOT: add
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@global.1 = local_unnamed_addr global i8 undef, align 1
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@global.2 = local_unnamed_addr global i8 undef, align 1
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define void @barney() #0 {
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bb:
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switch i8 undef, label %bb5 [
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i8 0, label %bb1
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i8 -1, label %bb2
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i8 1, label %bb3
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]
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bb1: ; preds = %bb
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store i8 -1, i8* @global.1, align 1
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unreachable
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bb2: ; preds = %bb
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store i8 -2, i8* @global.1, align 1
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unreachable
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bb3: ; preds = %bb
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store i8 -2, i8* @global.2, align 1
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store i8 -2, i8* @global.1, align 1
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unreachable
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bb5: ; preds = %bb
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ret void
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}
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; Test that for i16 type constant 65532 is not rebased if it's the only
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; dependent of base constant 65531. Cost would be the same if rebased.
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; If rebased, 3 two-byte instructions:
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; movs r0, #4
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; mvns r0, r0
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; adds r0, r0, #1
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; If NOT rebased, 1 two-byte instruction plus 1 four-byte CP entry:
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; ldr r1, .LCPI2_3
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; ...
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; .LCPI2_3:
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; .long 65532
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; OPT-LABEL: carla
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; -consthoist-min-num-to-rebase=1, check that 65532 and single use of 65531
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; in bb2 is rebased
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; OPT-1: bb1:
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; OPT-1: %[[C1:const[0-9]?]] = bitcast i16 -5 to i16
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; OPT-1-NEXT: %const_mat = add i16 %[[C1]], 1
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; OPT-1-NEXT: store i16 %const_mat, i16* @global.3, align 1
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; OPT-1: bb2:
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; OPT-1-NEXT: %[[C2:const[0-9]?]] = bitcast i16 -5 to i16
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; OPT-1-NEXT: store i16 %[[C2]], i16* @global.3, align 1
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; OPT-1: bb3:
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; OPT-1-NEXT: %[[C3:const[0-9]?]] = bitcast i16 -5 to i16
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; OPT-1-NEXT: store i16 %[[C3]], i16* @global.4, align 1
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; OPT-1-NEXT: store i16 %[[C3]], i16* @global.3, align 1
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; -consthoist-min-num-to-rebase=2, check that 65532 and single use of 65531
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; in bb2 is not rebased
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; OPT-2: bb1:
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; OPT-2-NEXT: store i16 -4, i16* @global.3, align 1
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; OPT-2: bb2:
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; OPT-2-NEXT: store i16 -5, i16* @global.3, align 1
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; OPT-2: bb3:
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; OPT-2-NEXT: %[[C4:const[0-9]?]] = bitcast i16 -5 to i16
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; OPT-2-NEXT: store i16 %[[C4]], i16* @global.4, align 1
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; OPT-2-NEXT: store i16 %[[C4]], i16* @global.3, align 1
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; OPT-2-NOT: add
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; -consthoist-min-num-to-rebase=3, check that dual uses of 65531 in bb3 are
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; not rebase
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; OPT-3: bb1:
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; OPT-3-NEXT: store i16 -4, i16* @global.3, align 1
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; OPT-3: bb2:
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; OPT-3-NEXT: store i16 -5, i16* @global.3, align 1
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; OPT-3: bb3:
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; OPT-3-NEXT: store i16 -5, i16* @global.4, align 1
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; OPT-3-NEXT: store i16 -5, i16* @global.3, align 1
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; OPT-3-NOT: add
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; OPT-3-NOT: bitcast
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; LLC-LABEL: carla
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; LLC-DAG: ldr r{{[0-9]+}}, .LCPI2_1
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; LLC-DAG: ldr r{{[0-9]+}}, .LCPI2_3
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; LLC-NOT: mvn
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; LLC-NOT: add
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@global.3 = local_unnamed_addr global i16 undef, align 2
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@global.4 = local_unnamed_addr global i16 undef, align 2
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define void @carla() {
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bb:
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switch i8 undef, label %bb5 [
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i8 0, label %bb1
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i8 -1, label %bb2
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i8 1, label %bb3
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]
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bb1: ; preds = %bb
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store i16 65532, i16* @global.3, align 1
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unreachable
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bb2: ; preds = %bb
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store i16 65531, i16* @global.3, align 1
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unreachable
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bb3: ; preds = %bb
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store i16 65531, i16* @global.4, align 1
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store i16 65531, i16* @global.3, align 1
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unreachable
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bb5: ; preds = %bb
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ret void
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}
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