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f6f0a5745d
We currently miss a number of opportunities to emit single-instruction VMRG[LH][BHW] instructions for shuffles on little endian subtargets. Although this in itself is not a huge performance opportunity since loading the permute vector for a VPERM can always be pulled out of loops, producing such merge instructions is useful to downstream optimizations. Since VPERM is essentially opaque to all subsequent optimizations, we want to avoid it as much as possible. Other permute instructions have semantics that can be reasoned about much more easily in later optimizations. This patch does the following: - Canonicalize shuffles so that the first element comes from the first vector (since that's what most of the mask matching functions want) - Switch the elements that come from splat vectors so that they match the corresponding elements from the other vector (to allow for merges) - Adds debugging messages for when a shuffle is matched to a VPERM so that anyone interested in improving this further can get the info for their code Differential revision: https://reviews.llvm.org/D77448
112 lines
3.9 KiB
LLVM
112 lines
3.9 KiB
LLVM
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -O3 < %s | FileCheck %s
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; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \
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; RUN: --implicit-check-not xxswapd
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; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mattr=-power9-vector < %s | FileCheck %s --check-prefix=CHECK-P9-NOVECTOR
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; These tests verify that VSX swap optimization works when loading a scalar
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; into a vector register.
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@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
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@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16
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@y = global double 1.780000e+00, align 8
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define void @bar0() {
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; CHECK-LABEL: bar0:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis r3, r2, .LC0@toc@ha
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; CHECK: addis r4, r2, .LC1@toc@ha
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; CHECK: ld r3, .LC0@toc@l(r3)
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; CHECK: addis r3, r2, .LC2@toc@ha
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; CHECK: ld r3, .LC2@toc@l(r3)
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; CHECK: xxmrgld vs0, vs0, vs1
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; CHECK: stxvd2x vs0, 0, r3
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; CHECK: blr
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;
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; CHECK-P9-NOVECTOR-LABEL: bar0:
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; CHECK-P9-NOVECTOR: # %bb.0: # %entry
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC0@toc@ha
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; CHECK-P9-NOVECTOR: ld r3, .LC0@toc@l(r3)
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC1@toc@ha
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC2@toc@ha
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; CHECK-P9-NOVECTOR: ld r3, .LC2@toc@l(r3)
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; CHECK-P9-NOVECTOR: xxmrgld vs0, vs1, vs0
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; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3
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; CHECK-P9-NOVECTOR: blr
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;
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; CHECK-P9-LABEL: bar0:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9: addis r3, r2, .LC0@toc@ha
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; CHECK-P9: ld r3, .LC0@toc@l(r3)
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; CHECK-P9: lxvx vs0, 0, r3
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; CHECK-P9: addis r3, r2, .LC1@toc@ha
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; CHECK-P9: ld r3, .LC1@toc@l(r3)
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; CHECK-P9: lfd f1, 0(r3)
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; CHECK-P9: addis r3, r2, .LC2@toc@ha
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; CHECK-P9: ld r3, .LC2@toc@l(r3)
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; CHECK-P9: xxswapd vs1, f1
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; CHECK-P9: xxpermdi vs0, vs0, vs1, 1
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; CHECK-P9: stxvx vs0, 0, r3
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; CHECK-P9: blr
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entry:
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%0 = load <2 x double>, <2 x double>* @x, align 16
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%1 = load double, double* @y, align 8
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%vecins = insertelement <2 x double> %0, double %1, i32 0
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store <2 x double> %vecins, <2 x double>* @z, align 16
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ret void
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}
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define void @bar1() {
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; CHECK-LABEL: bar1:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis r3, r2, .LC0@toc@ha
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; CHECK: addis r4, r2, .LC1@toc@ha
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; CHECK: ld r3, .LC0@toc@l(r3)
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; CHECK: addis r3, r2, .LC2@toc@ha
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; CHECK: ld r3, .LC2@toc@l(r3)
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; CHECK: xxpermdi vs0, vs1, vs0, 1
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; CHECK: stxvd2x vs0, 0, r3
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; CHECK: blr
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;
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; CHECK-P9-NOVECTOR-LABEL: bar1:
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; CHECK-P9-NOVECTOR: # %bb.0: # %entry
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC0@toc@ha
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; CHECK-P9-NOVECTOR: ld r3, .LC0@toc@l(r3)
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC1@toc@ha
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC2@toc@ha
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; CHECK-P9-NOVECTOR: ld r3, .LC2@toc@l(r3)
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; CHECK-P9-NOVECTOR: xxpermdi vs0, vs0, vs1, 1
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; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3
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; CHECK-P9-NOVECTOR: blr
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;
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; CHECK-P9-LABEL: bar1:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9: addis r3, r2, .LC0@toc@ha
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; CHECK-P9: ld r3, .LC0@toc@l(r3)
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; CHECK-P9: lxvx vs0, 0, r3
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; CHECK-P9: addis r3, r2, .LC1@toc@ha
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; CHECK-P9: ld r3, .LC1@toc@l(r3)
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; CHECK-P9: lfd f1, 0(r3)
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; CHECK-P9: addis r3, r2, .LC2@toc@ha
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; CHECK-P9: ld r3, .LC2@toc@l(r3)
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; CHECK-P9: xxswapd vs1, f1
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; CHECK-P9: xxmrgld vs0, vs1, vs0
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; CHECK-P9: stxvx vs0, 0, r3
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; CHECK-P9: blr
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entry:
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%0 = load <2 x double>, <2 x double>* @x, align 16
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%1 = load double, double* @y, align 8
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%vecins = insertelement <2 x double> %0, double %1, i32 1
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store <2 x double> %vecins, <2 x double>* @z, align 16
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ret void
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}
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